Update synth scripts after abc9 cli change

YosysHQ · Mar 14, 2024 · b1345cb · b1345cb
1 parent 09919fe
commit b1345cb
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Showing 7 changed files with 9 additions and 9 deletions.
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
@@ -388,7 +388,7 @@ struct SynthEcp5Pass : public ScriptPass
 					abc9_opts += " -maxlut 4";
 				if (dff)
 					abc9_opts += " -dff";
-				run("abc9" + abc9_opts);
+				run("abc9 -lutlib" + abc9_opts);
 			} else {
 				std::string abc_args = " -dress";
 				if (nowidelut)

diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
@@ -278,12 +278,12 @@ struct SynthGowinPass : public ScriptPass
 		{
 			if (nowidelut && abc9) {
 				run("read_verilog -icells -lib -specify +/abc9_model.v");
-				run("abc9 -maxlut 4 -W 500");
+				run("abc9 -lutlib -maxlut 4 -W 500");
 			} else if (nowidelut && !abc9) {
 				run("abc -lut 4");
 			} else if (!nowidelut && abc9) {
 				run("read_verilog -icells -lib -specify +/abc9_model.v");
-				run("abc9 -maxlut 8 -W 500");
+				run("abc9 -lutlib -maxlut 8 -W 500");
 			} else if (!nowidelut && !abc9) {
 				run("abc -lut 4:8");
 			}

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
@@ -424,7 +424,7 @@ struct SynthIce40Pass : public ScriptPass
 					}
 					if (dff)
 						abc9_opts += " -dff";
-					run("abc9 " + abc9_opts);
+					run("abc9 -lutlib" + abc9_opts);
 				}
 				else
 					run(stringf("abc -dress -lut 4 %s", dff ? "-dff" : ""), "(skip if -noabc)");

diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc
@@ -454,7 +454,7 @@ struct SynthLatticePass : public ScriptPass
 					abc9_opts += " -maxlut 4";
 				if (dff)
 					abc9_opts += " -dff";
-				run("abc9" + abc9_opts);
+				run("abc9 -lutlib" + abc9_opts);
 			} else {
 				std::string abc_args = " -dress";
 				if (nowidelut)

diff --git a/techlibs/nexus/synth_nexus.cc b/techlibs/nexus/synth_nexus.cc
@@ -366,7 +366,7 @@ struct SynthNexusPass : public ScriptPass
 					abc9_opts += " -maxlut 4";
 				if (dff)
 					abc9_opts += " -dff";
-				run("abc9" + abc9_opts);
+				run("abc9 -lutlib" + abc9_opts);
 			} else {
 				std::string abc_args = " -dress";
 				if (nowidelut)

diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc
@@ -304,7 +304,7 @@ struct SynthQuickLogicPass : public ScriptPass {
 			if (abc9) {
 				run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v");
 				run("techmap -map " + lib_path + family + "/abc9_map.v");
-				run("abc9 -maxlut 4 -dff");
+				run("abc9 -lutlib -maxlut 4 -dff");
 				run("techmap -map " + lib_path + family + "/abc9_unmap.v");
 			} else {
 				run("abc -luts 1,2,2,4 -dress");
@@ -314,7 +314,7 @@ struct SynthQuickLogicPass : public ScriptPass {
 
 		if (check_label("map_luts", "(for qlf_k6n10f)") && (help_mode || family == "qlf_k6n10f")) {
 			if (abc9) {
-				run("abc9 -maxlut 6");
+				run("abc9 -lutlib -maxlut 6");
 			} else {
 				run("abc -lut 6 -dress");
 			}

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
@@ -650,7 +650,7 @@ struct SynthXilinxPass : public ScriptPass
 					abc9_opts += stringf(" -maxlut %d", lut_size);
 				if (dff)
 					abc9_opts += " -dff";
-				run("abc9" + abc9_opts);
+				run("abc9 -lutlib" + abc9_opts);
 			}
 			else {
 				std::string abc_opts;