Add test_cell tests for C++ functional backend

backends/functional/cxx.cc

@@ -17,6 +17,7 @@
  *
  */
 
+#include <cassert>
 #include "kernel/yosys.h"
 #include "kernel/drivertools.h"
 #include "kernel/topo_scc.h"
@@ -96,31 +97,70 @@ struct CxxWriter {
 };
 
 struct CxxStruct {
-	std::string name;
-	dict<IdString, std::string> types;
-	CxxScope scope;
-	CxxStruct(std::string name) : name(name) {
-		scope.reserve("out");
-		scope.reserve("dump");
-	}
-	void insert(IdString name, std::string type) {
-		scope.insert(name);
-		types.insert({name, type});
-	}
-	void print(CxxWriter &f) {
-		f.printf("struct %s {\n", name.c_str());
-		for (auto p : types) {
-			f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str());
-		}
-		f.printf("\n\ttemplate <typename T> void dump(T &out) {\n");
-		for (auto p : types) {
-			f.printf("\t\tout(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope[p.first].c_str());
-		}
-		f.printf("\t}\n};\n\n");
-	}
-	std::string operator[](IdString field) {
-		return scope[field];
-	}
+  std::string name;
+  dict<IdString, std::string> types;
+  CxxScope scope;
+  bool generate_methods;
+  int count;
+  CxxStruct(std::string name, bool generate_methods = false, int count = 0) 
+    : name(name), generate_methods(generate_methods), count(count) {
+    scope.reserve("out");
+    scope.reserve("dump");
+  }
+  void insert(IdString name, std::string type) {
+    scope.insert(name);
+    types.insert({name, type});
+  }
+  void print(CxxWriter &f) {
+    f.printf("struct %s {\n", name.c_str());
+    for (auto p : types) {
+      f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str());
+    }
+    f.printf("\n\ttemplate <typename T> void dump(T &out) const {\n");
+    for (auto p : types) {
+      f.printf("\t\tout(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope[p.first].c_str());
+    }
+    f.printf("\t}\n\n");
+
+    if (generate_methods) {
+      // Add size method
+      f.printf("\tint size() const {\n");
+      f.printf("\t\treturn %d;\n", count);
+      f.printf("\t}\n\n");
+
+      // Add get_input method
+      f.printf("\tstd::variant<%s> get_input(const int index) {\n", generate_variant_types().c_str());
+      f.printf("\t\tswitch (index) {\n");
+      int idx = 0;
+      for (auto p : types) {
+	f.printf("\t\t\tcase %d: return std::ref(%s);\n", idx, scope[p.first].c_str());
+	idx++;
+      }
+      f.printf("\t\t\tdefault: throw std::out_of_range(\"Invalid input index\");\n");
+      f.printf("\t\t}\n");
+      f.printf("\t}\n");
+    }
+
+    f.printf("};\n\n");
+  };
+  std::string operator[](IdString field) {
+    return scope[field];
+  }
+  private:
+  std::string generate_variant_types() const {
+        std::set<std::string> unique_types;
+        for (const auto& p : types) {
+            unique_types.insert("std::reference_wrapper<" + p.second + ">");
+        }
+        std::ostringstream oss;
+        for (auto it = unique_types.begin(); it != unique_types.end(); ++it) {
+            if (it != unique_types.begin()) {
+                oss << ", ";
+            }
+            oss << *it;
+        }
+        return oss.str();
+  }
 };
 
 struct CxxFunction {
@@ -302,7 +342,8 @@ struct FunctionalCxxBackend : public Backend
 				state[ref.function().parameters.begin()->first] = ref.function().width;
 		}
 		f.printf("#include \"sim.h\"\n");
-		CxxStruct input_struct(name + "_Inputs");
+		f.printf("#include <variant>\n");
+		CxxStruct input_struct(name + "_Inputs", true, inputs.size());
 		for (auto const &input : inputs)
 			input_struct.insert(input.first, "Signal<" + std::to_string(input.second) + ">");
 		CxxStruct output_struct(name + "_Outputs");

backends/functional/cxx_runtime/sim.h

@@ -20,6 +20,7 @@
 #ifndef SIM_H
 #define SIM_H
 
+#include <cassert>
 #include <array>
 
 template<size_t n>

backends/functional/smtlib.cc

@@ -17,6 +17,7 @@
  *
  */
 
+#include <cassert>
 #include "kernel/yosys.h"
 #include "kernel/drivertools.h"
 #include "kernel/topo_scc.h"

tests/functional/.gitignore

@@ -0,0 +1,4 @@
+my_module_cxxrtl.cc
+my_module_functional_cxx.cc
+vcd_harness
+*.vcd

tests/functional/single_cells/rtlil/test_cell_add_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 5 input 1 \A
+  wire width 4 input 2 \B
+  wire width 6 output 3 \Y
+  cell $add \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_alu_00000.il

@@ -0,0 +1,25 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire width 7 input 2 \B
+  wire input 3 \BI
+  wire input 4 \CI
+  wire width 6 output 5 \CO
+  wire width 6 output 6 \X
+  wire width 6 output 7 \Y
+  cell $alu \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \BI \BI
+    connect \CI \CI
+    connect \CO \CO
+    connect \X \X
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_and_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 2 input 1 \A
+  wire width 3 input 2 \B
+  wire width 2 output 3 \Y
+  cell $and \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_bmux_00000.il

@@ -0,0 +1,14 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire input 2 \S
+  wire width 4 output 3 \Y
+  cell $bmux \UUT
+    parameter \S_WIDTH 1
+    parameter \WIDTH 4
+    connect \A \A
+    connect \S \S
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_demux_00000.il

@@ -0,0 +1,14 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 6 input 1 \A
+  wire width 5 input 2 \S
+  wire width 192 output 3 \Y
+  cell $demux \UUT
+    parameter \S_WIDTH 5
+    parameter \WIDTH 6
+    connect \A \A
+    connect \S \S
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_div_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire width 6 input 2 \B
+  wire output 3 \Y
+  cell $div \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 1
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire width 4 input 2 \B
+  wire width 6 output 3 \Y
+  cell $divfloor \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_eq_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 5 input 1 \A
+  wire input 2 \B
+  wire width 4 output 3 \Y
+  cell $eq \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_fa_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \A
+  wire input 2 \B
+  wire input 3 \C
+  wire output 4 \X
+  wire output 5 \Y
+  cell $fa \UUT
+    parameter \WIDTH 1
+    connect \A \A
+    connect \B \B
+    connect \C \C
+    connect \X \X
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_ge_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 3 input 1 \A
+  wire width 7 input 2 \B
+  wire width 6 output 3 \Y
+  cell $ge \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_gt_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire width 3 input 2 \B
+  wire width 4 output 3 \Y
+  cell $gt \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_lcu_00000.il

@@ -0,0 +1,15 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \CI
+  wire width 2 output 2 \CO
+  wire width 2 input 3 \G
+  wire width 2 input 4 \P
+  cell $lcu \UUT
+    parameter \WIDTH 2
+    connect \CI \CI
+    connect \CO \CO
+    connect \G \G
+    connect \P \P
+  end
+end

tests/functional/single_cells/rtlil/test_cell_le_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 5 input 1 \A
+  wire width 4 input 2 \B
+  wire width 6 output 3 \Y
+  cell $le \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 2 input 1 \A
+  wire width 7 input 2 \B
+  wire output 3 \Y
+  cell $logic_and \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 1
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end