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Add test_cell tests for C++ functional backend
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49 files changed

+963
-26
lines changed

‎backends/functional/cxx.cc

+67-26
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717
*
1818
*/
1919

20+
#include <cassert>
2021
#include "kernel/yosys.h"
2122
#include "kernel/drivertools.h"
2223
#include "kernel/topo_scc.h"
@@ -96,31 +97,70 @@ struct CxxWriter {
9697
};
9798

9899
struct CxxStruct {
99-
std::string name;
100-
dict<IdString, std::string> types;
101-
CxxScope scope;
102-
CxxStruct(std::string name) : name(name) {
103-
scope.reserve("out");
104-
scope.reserve("dump");
105-
}
106-
void insert(IdString name, std::string type) {
107-
scope.insert(name);
108-
types.insert({name, type});
109-
}
110-
void print(CxxWriter &f) {
111-
f.printf("struct %s {\n", name.c_str());
112-
for (auto p : types) {
113-
f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str());
114-
}
115-
f.printf("\n\ttemplate <typename T> void dump(T &out) {\n");
116-
for (auto p : types) {
117-
f.printf("\t\tout(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope[p.first].c_str());
118-
}
119-
f.printf("\t}\n};\n\n");
120-
}
121-
std::string operator[](IdString field) {
122-
return scope[field];
123-
}
100+
std::string name;
101+
dict<IdString, std::string> types;
102+
CxxScope scope;
103+
bool generate_methods;
104+
int count;
105+
CxxStruct(std::string name, bool generate_methods = false, int count = 0)
106+
: name(name), generate_methods(generate_methods), count(count) {
107+
scope.reserve("out");
108+
scope.reserve("dump");
109+
}
110+
void insert(IdString name, std::string type) {
111+
scope.insert(name);
112+
types.insert({name, type});
113+
}
114+
void print(CxxWriter &f) {
115+
f.printf("struct %s {\n", name.c_str());
116+
for (auto p : types) {
117+
f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str());
118+
}
119+
f.printf("\n\ttemplate <typename T> void dump(T &out) const {\n");
120+
for (auto p : types) {
121+
f.printf("\t\tout(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope[p.first].c_str());
122+
}
123+
f.printf("\t}\n\n");
124+
125+
if (generate_methods) {
126+
// Add size method
127+
f.printf("\tint size() const {\n");
128+
f.printf("\t\treturn %d;\n", count);
129+
f.printf("\t}\n\n");
130+
131+
// Add get_input method
132+
f.printf("\tstd::variant<%s> get_input(const int index) {\n", generate_variant_types().c_str());
133+
f.printf("\t\tswitch (index) {\n");
134+
int idx = 0;
135+
for (auto p : types) {
136+
f.printf("\t\t\tcase %d: return std::ref(%s);\n", idx, scope[p.first].c_str());
137+
idx++;
138+
}
139+
f.printf("\t\t\tdefault: throw std::out_of_range(\"Invalid input index\");\n");
140+
f.printf("\t\t}\n");
141+
f.printf("\t}\n");
142+
}
143+
144+
f.printf("};\n\n");
145+
};
146+
std::string operator[](IdString field) {
147+
return scope[field];
148+
}
149+
private:
150+
std::string generate_variant_types() const {
151+
std::set<std::string> unique_types;
152+
for (const auto& p : types) {
153+
unique_types.insert("std::reference_wrapper<" + p.second + ">");
154+
}
155+
std::ostringstream oss;
156+
for (auto it = unique_types.begin(); it != unique_types.end(); ++it) {
157+
if (it != unique_types.begin()) {
158+
oss << ", ";
159+
}
160+
oss << *it;
161+
}
162+
return oss.str();
163+
}
124164
};
125165

126166
struct CxxFunction {
@@ -302,7 +342,8 @@ struct FunctionalCxxBackend : public Backend
302342
state[ref.function().parameters.begin()->first] = ref.function().width;
303343
}
304344
f.printf("#include \"sim.h\"\n");
305-
CxxStruct input_struct(name + "_Inputs");
345+
f.printf("#include <variant>\n");
346+
CxxStruct input_struct(name + "_Inputs", true, inputs.size());
306347
for (auto const &input : inputs)
307348
input_struct.insert(input.first, "Signal<" + std::to_string(input.second) + ">");
308349
CxxStruct output_struct(name + "_Outputs");

‎backends/functional/cxx_runtime/sim.h

+1
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@@ -20,6 +20,7 @@
2020
#ifndef SIM_H
2121
#define SIM_H
2222

23+
#include <cassert>
2324
#include <array>
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2526
template<size_t n>

‎backends/functional/smtlib.cc

+1
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@@ -17,6 +17,7 @@
1717
*
1818
*/
1919

20+
#include <cassert>
2021
#include "kernel/yosys.h"
2122
#include "kernel/drivertools.h"
2223
#include "kernel/topo_scc.h"

‎tests/functional/.gitignore

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my_module_cxxrtl.cc
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my_module_functional_cxx.cc
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vcd_harness
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*.vcd

‎tests/functional/single_cells/rtlil/test_cell_add_00000.il

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# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
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autoidx 1
3+
module \gold
4+
wire width 5 input 1 \A
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wire width 4 input 2 \B
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wire width 6 output 3 \Y
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cell $add \UUT
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parameter \A_SIGNED 1
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parameter \A_WIDTH 5
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parameter \B_SIGNED 1
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parameter \B_WIDTH 4
12+
parameter \Y_WIDTH 6
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connect \A \A
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connect \B \B
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connect \Y \Y
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end
17+
end

‎tests/functional/single_cells/rtlil/test_cell_alu_00000.il

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# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
2+
autoidx 1
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module \gold
4+
wire width 8 input 1 \A
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wire width 7 input 2 \B
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wire input 3 \BI
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wire input 4 \CI
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wire width 6 output 5 \CO
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wire width 6 output 6 \X
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wire width 6 output 7 \Y
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cell $alu \UUT
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parameter \A_SIGNED 0
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parameter \A_WIDTH 8
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parameter \B_SIGNED 0
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parameter \B_WIDTH 7
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parameter \Y_WIDTH 6
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connect \A \A
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connect \B \B
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connect \BI \BI
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connect \CI \CI
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connect \CO \CO
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connect \X \X
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connect \Y \Y
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end
25+
end

‎tests/functional/single_cells/rtlil/test_cell_and_00000.il

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# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
2+
autoidx 1
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module \gold
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wire width 2 input 1 \A
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wire width 3 input 2 \B
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wire width 2 output 3 \Y
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cell $and \UUT
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parameter \A_SIGNED 1
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parameter \A_WIDTH 2
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parameter \B_SIGNED 1
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parameter \B_WIDTH 3
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parameter \Y_WIDTH 2
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connect \A \A
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connect \B \B
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connect \Y \Y
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end
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end

‎tests/functional/single_cells/rtlil/test_cell_bmux_00000.il

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1+
# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
2+
autoidx 1
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module \gold
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wire width 8 input 1 \A
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wire input 2 \S
6+
wire width 4 output 3 \Y
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cell $bmux \UUT
8+
parameter \S_WIDTH 1
9+
parameter \WIDTH 4
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connect \A \A
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connect \S \S
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connect \Y \Y
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end
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end

‎tests/functional/single_cells/rtlil/test_cell_demux_00000.il

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# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
2+
autoidx 1
3+
module \gold
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wire width 6 input 1 \A
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wire width 5 input 2 \S
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wire width 192 output 3 \Y
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cell $demux \UUT
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parameter \S_WIDTH 5
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parameter \WIDTH 6
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connect \A \A
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connect \S \S
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connect \Y \Y
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end
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end

‎tests/functional/single_cells/rtlil/test_cell_div_00000.il

+17
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@@ -0,0 +1,17 @@
1+
# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
2+
autoidx 1
3+
module \gold
4+
wire width 4 input 1 \A
5+
wire width 6 input 2 \B
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wire output 3 \Y
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cell $div \UUT
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parameter \A_SIGNED 0
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parameter \A_WIDTH 4
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parameter \B_SIGNED 0
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parameter \B_WIDTH 6
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parameter \Y_WIDTH 1
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connect \A \A
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connect \B \B
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connect \Y \Y
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end
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end

‎tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il

+17
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@@ -0,0 +1,17 @@
1+
# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
2+
autoidx 1
3+
module \gold
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wire width 4 input 1 \A
5+
wire width 4 input 2 \B
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wire width 6 output 3 \Y
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cell $divfloor \UUT
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parameter \A_SIGNED 0
9+
parameter \A_WIDTH 4
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parameter \B_SIGNED 0
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parameter \B_WIDTH 4
12+
parameter \Y_WIDTH 6
13+
connect \A \A
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connect \B \B
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connect \Y \Y
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end
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end

‎tests/functional/single_cells/rtlil/test_cell_eq_00000.il

+17
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@@ -0,0 +1,17 @@
1+
# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
2+
autoidx 1
3+
module \gold
4+
wire width 5 input 1 \A
5+
wire input 2 \B
6+
wire width 4 output 3 \Y
7+
cell $eq \UUT
8+
parameter \A_SIGNED 0
9+
parameter \A_WIDTH 5
10+
parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 4
13+
connect \A \A
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connect \B \B
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connect \Y \Y
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end
17+
end

‎tests/functional/single_cells/rtlil/test_cell_fa_00000.il

+17
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@@ -0,0 +1,17 @@
1+
# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
2+
autoidx 1
3+
module \gold
4+
wire input 1 \A
5+
wire input 2 \B
6+
wire input 3 \C
7+
wire output 4 \X
8+
wire output 5 \Y
9+
cell $fa \UUT
10+
parameter \WIDTH 1
11+
connect \A \A
12+
connect \B \B
13+
connect \C \C
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connect \X \X
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connect \Y \Y
16+
end
17+
end

‎tests/functional/single_cells/rtlil/test_cell_ge_00000.il

+17
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@@ -0,0 +1,17 @@
1+
# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
2+
autoidx 1
3+
module \gold
4+
wire width 3 input 1 \A
5+
wire width 7 input 2 \B
6+
wire width 6 output 3 \Y
7+
cell $ge \UUT
8+
parameter \A_SIGNED 1
9+
parameter \A_WIDTH 3
10+
parameter \B_SIGNED 1
11+
parameter \B_WIDTH 7
12+
parameter \Y_WIDTH 6
13+
connect \A \A
14+
connect \B \B
15+
connect \Y \Y
16+
end
17+
end

‎tests/functional/single_cells/rtlil/test_cell_gt_00000.il

+17
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@@ -0,0 +1,17 @@
1+
# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
2+
autoidx 1
3+
module \gold
4+
wire width 7 input 1 \A
5+
wire width 3 input 2 \B
6+
wire width 4 output 3 \Y
7+
cell $gt \UUT
8+
parameter \A_SIGNED 1
9+
parameter \A_WIDTH 7
10+
parameter \B_SIGNED 1
11+
parameter \B_WIDTH 3
12+
parameter \Y_WIDTH 4
13+
connect \A \A
14+
connect \B \B
15+
connect \Y \Y
16+
end
17+
end

‎tests/functional/single_cells/rtlil/test_cell_lcu_00000.il

+15
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@@ -0,0 +1,15 @@
1+
# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
2+
autoidx 1
3+
module \gold
4+
wire input 1 \CI
5+
wire width 2 output 2 \CO
6+
wire width 2 input 3 \G
7+
wire width 2 input 4 \P
8+
cell $lcu \UUT
9+
parameter \WIDTH 2
10+
connect \CI \CI
11+
connect \CO \CO
12+
connect \G \G
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connect \P \P
14+
end
15+
end

‎tests/functional/single_cells/rtlil/test_cell_le_00000.il

+17
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@@ -0,0 +1,17 @@
1+
# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
2+
autoidx 1
3+
module \gold
4+
wire width 5 input 1 \A
5+
wire width 4 input 2 \B
6+
wire width 6 output 3 \Y
7+
cell $le \UUT
8+
parameter \A_SIGNED 1
9+
parameter \A_WIDTH 5
10+
parameter \B_SIGNED 1
11+
parameter \B_WIDTH 4
12+
parameter \Y_WIDTH 6
13+
connect \A \A
14+
connect \B \B
15+
connect \Y \Y
16+
end
17+
end

‎tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il

+17
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@@ -0,0 +1,17 @@
1+
# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
2+
autoidx 1
3+
module \gold
4+
wire width 2 input 1 \A
5+
wire width 7 input 2 \B
6+
wire output 3 \Y
7+
cell $logic_and \UUT
8+
parameter \A_SIGNED 0
9+
parameter \A_WIDTH 2
10+
parameter \B_SIGNED 0
11+
parameter \B_WIDTH 7
12+
parameter \Y_WIDTH 1
13+
connect \A \A
14+
connect \B \B
15+
connect \Y \Y
16+
end
17+
end

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