Preserve VHDL architecture name in attribute

YosysHQ · Oct 12, 2023 · d473a20 · d473a20
1 parent 59fbee4
commit d473a20
Showing 1 changed file with 8 additions and 0 deletions.
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
@@ -52,6 +52,7 @@ USING_YOSYS_NAMESPACE
 #ifdef VERIFIC_VHDL_SUPPORT
 #include "vhdl_file.h"
 #include "VhdlUnits.h"
+#include "NameSpace.h"
 #endif
 
 #ifdef VERIFIC_EDIF_SUPPORT
@@ -1276,6 +1277,13 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 	}
 	import_attributes(module->attributes, nl, nl);
 	module->set_string_attribute(ID::hdlname, nl->CellBaseName());
+#ifdef VERIFIC_VHDL_SUPPORT
+	if (nl->IsFromVhdl()) {
+		NameSpace name_space(0);
+		char *architecture_name = name_space.ReName(nl->Name()) ;
+		module->set_string_attribute(ID(architecture), (architecture_name) ? architecture_name : nl->Name());
+	}
+#endif	
 	const char *param_name ;
 	const char *param_value ;
 	MapIter mi;