Merge pull request #4506 from povik/synthprop-formatting

synthprop: Reformat the help

passes/sat/synthprop.cc

@@ -185,35 +185,25 @@ struct SyntProperties : public Pass {
 		log("\n");
 		log("    synthprop [options]\n");
 		log("\n");
-		log("This creates synthesizable properties for selected module.\n");
+		log("This creates synthesizable properties for the selected module.\n");
 		log("\n");
 		log("\n");
 		log("    -name <portname>\n");
-		log("\n");
-		log("Name output port for assertions (default: assertions).\n");
-		log("\n");
+		log("        name of the output port for assertions (default: assertions).\n");
 		log("\n");
 		log("    -map <filename>\n");
-		log("\n");
-		log("Write port mapping for synthesizable properties.\n");
-		log("\n");
+		log("        write the port mapping for synthesizable properties into the given file.\n");
 		log("\n");
 		log("    -or_outputs\n");
-		log("\n");
-		log("Or all outputs together to create a single output that goes high when any\n");
-		log("property is violated, instead of generating individual output bits.\n");
-		log("\n");
+		log("        Or all outputs together to create a single output that goes high when\n");
+		log("        any property is violated, instead of generating individual output bits.\n");
 		log("\n");
 		log("    -reset <portname>\n");
-		log("\n");
-		log("Name of top-level reset input. Latch a high state on the generated outputs\n");
-		log("until an asynchronous top-level reset input is activated.\n");
-		log("\n");
+		log("        name of the top-level reset input. Latch a high state on the generated\n");
+		log("        outputs until an asynchronous top-level reset input is activated.\n");
 		log("\n");
 		log("    -resetn <portname>\n");
-		log("\n");
-		log("Name of top-level reset input (inverse polarity). Latch a high state on the\n");
-		log("generated outputs until an asynchronous top-level reset input is activated.\n");
+		log("        like above but with inverse polarity\n");
 		log("\n");
 		log("\n");
 	}