fixup! quicklogic: Add basic k6n10f tests

YosysHQ · Nov 29, 2023 · e70122b · e70122b
1 parent 6066115
commit e70122b
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Showing 2 changed files with 11 additions and 33 deletions.
diff --git a/tests/arch/quicklogic/qlf_k6n10f/latches.ys b/tests/arch/quicklogic/qlf_k6n10f/latches.ys
@@ -3,32 +3,27 @@ design -save read
 
 hierarchy -top latchp
 proc
-# Can't run any sort of equivalence check because latches are blown to LUTs
-synth_quicklogic -family qlf_k6n10f
-cd latchp # Constrain all select calls below inside the top module
+equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f
+design -load postopt
+cd latchp
 select -assert-count 1 t:latchsre
-
 select -assert-none t:latchsre %% t:* %D
 
-
 design -load read
 hierarchy -top latchn
 proc
-# Can't run any sort of equivalence check because latches are blown to LUTs
-synth_quicklogic -family qlf_k6n10f
-cd latchn # Constrain all select calls below inside the top module
+equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f
+design -load postopt
+cd latchn
 select -assert-count 1 t:latchnsre
-
 select -assert-none t:latchnsre %% t:* %D
 
-
 design -load read
 hierarchy -top latchsr
 proc
-# Can't run any sort of equivalence check because latches are blown to LUTs
-synth_quicklogic -family qlf_k6n10f
-cd latchsr # Constrain all select calls below inside the top module
+equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f
+design -load postopt
+cd latchsr
 select -assert-count 2 t:$lut
-select -assert-count 1 t:dffsr
-
-select -assert-none t:$lut t:dffsr %% t:* %D
+select -assert-count 1 t:latchnsre
+select -assert-none t:$lut t:latchnsre %% t:* %D
diff --git a/tests/arch/quicklogic/qlf_k6n10f/test.ys b/tests/arch/quicklogic/qlf_k6n10f/test.ys