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Revert formatting changes.
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@rmlarsen
rmlarsen committed Sep 29, 2023
1 parent 3dadd29 commit fdb044e
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Showing 2 changed files with 235 additions and 239 deletions.
200 changes: 92 additions & 108 deletions passes/techmap/simplemap.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -18,10 +18,10 @@
*/

#include "simplemap.h"
#include "kernel/ff.h"
#include "kernel/sigtools.h"
#include <stdio.h>
#include "kernel/ff.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>

USING_YOSYS_NAMESPACE
Expand Down Expand Up @@ -64,16 +64,11 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
}

IdString gate_type;
if (cell->type == ID($and))
gate_type = ID($_AND_);
if (cell->type == ID($or))
gate_type = ID($_OR_);
if (cell->type == ID($xor))
gate_type = ID($_XOR_);
if (cell->type == ID($xnor))
gate_type = ID($_XNOR_);
if (cell->type == ID($bweqx))
gate_type = ID($_XNOR_);
if (cell->type == ID($and)) gate_type = ID($_AND_);
if (cell->type == ID($or)) gate_type = ID($_OR_);
if (cell->type == ID($xor)) gate_type = ID($_XOR_);
if (cell->type == ID($xnor)) gate_type = ID($_XNOR_);
if (cell->type == ID($bweqx)) gate_type = ID($_XNOR_);
log_assert(!gate_type.empty());

for (int i = 0; i < GetSize(sig_y); i++) {
Expand All @@ -94,53 +89,45 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
return;

if (sig_a.size() == 0) {
if (cell->type == ID($reduce_and))
module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
if (cell->type == ID($reduce_or))
module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
if (cell->type == ID($reduce_xor))
module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
if (cell->type == ID($reduce_xnor))
module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
if (cell->type == ID($reduce_bool))
module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
if (cell->type == ID($reduce_and)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
if (cell->type == ID($reduce_or)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
if (cell->type == ID($reduce_xor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
if (cell->type == ID($reduce_xnor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
if (cell->type == ID($reduce_bool)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
return;
}

if (sig_y.size() > 1) {
module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size() - 1), RTLIL::SigSpec(0, sig_y.size() - 1)));
module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
sig_y = sig_y.extract(0, 1);
}

IdString gate_type;
if (cell->type == ID($reduce_and))
gate_type = ID($_AND_);
if (cell->type == ID($reduce_or))
gate_type = ID($_OR_);
if (cell->type == ID($reduce_xor))
gate_type = ID($_XOR_);
if (cell->type == ID($reduce_xnor))
gate_type = ID($_XOR_);
if (cell->type == ID($reduce_bool))
gate_type = ID($_OR_);
if (cell->type == ID($reduce_and)) gate_type = ID($_AND_);
if (cell->type == ID($reduce_or)) gate_type = ID($_OR_);
if (cell->type == ID($reduce_xor)) gate_type = ID($_XOR_);
if (cell->type == ID($reduce_xnor)) gate_type = ID($_XOR_);
if (cell->type == ID($reduce_bool)) gate_type = ID($_OR_);
log_assert(!gate_type.empty());

RTLIL::Cell *last_output_cell = NULL;

while (sig_a.size() > 1) {
while (sig_a.size() > 1)
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2);

for (int i = 0; i < sig_a.size(); i += 2) {
if (i + 1 == sig_a.size()) {
for (int i = 0; i < sig_a.size(); i += 2)
{
if (i+1 == sig_a.size()) {
sig_t.append(sig_a[i]);
continue;
}

RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_a[i + 1]);
gate->setPort(ID::Y, sig_t[i / 2]);
gate->setPort(ID::B, sig_a[i+1]);
gate->setPort(ID::Y, sig_t[i/2]);
last_output_cell = gate;
}

Expand All @@ -166,20 +153,22 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)

static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell *cell)
{
while (sig.size() > 1) {
while (sig.size() > 1)
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2);

for (int i = 0; i < sig.size(); i += 2) {
if (i + 1 == sig.size()) {
for (int i = 0; i < sig.size(); i += 2)
{
if (i+1 == sig.size()) {
sig_t.append(sig[i]);
continue;
}

RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig[i]);
gate->setPort(ID::B, sig[i + 1]);
gate->setPort(ID::Y, sig_t[i / 2]);
gate->setPort(ID::B, sig[i+1]);
gate->setPort(ID::Y, sig_t[i/2]);
}

sig = sig_t;
Expand All @@ -200,7 +189,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
return;

if (sig_y.size() > 1) {
module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size() - 1), RTLIL::SigSpec(0, sig_y.size() - 1)));
module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
sig_y = sig_y.extract(0, 1);
}

Expand All @@ -224,15 +213,13 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
return;

if (sig_y.size() > 1) {
module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size() - 1), RTLIL::SigSpec(0, sig_y.size() - 1)));
module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
sig_y = sig_y.extract(0, 1);
}

IdString gate_type;
if (cell->type == ID($logic_and))
gate_type = ID($_AND_);
if (cell->type == ID($logic_or))
gate_type = ID($_OR_);
if (cell->type == ID($logic_and)) gate_type = ID($_AND_);
if (cell->type == ID($logic_or)) gate_type = ID($_OR_);
log_assert(!gate_type.empty());

RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
Expand All @@ -253,22 +240,19 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
xor_cell->attributes[ID::src] = cell->attributes[ID::src];
// xor_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
simplemap_bitop(module, xor_cell);
module->remove(xor_cell);

RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
reduce_cell->attributes[ID::src] = cell->attributes[ID::src];
// reduce_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
simplemap_reduce(module, reduce_cell);
module->remove(reduce_cell);

if (!is_ne) {
RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y);
not_cell->attributes[ID::src] = cell->attributes[ID::src];
// not_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
simplemap_lognot(module, not_cell);
simplemap_lognot(module, not_cell);
module->remove(not_cell);
}
}
Expand Down Expand Up @@ -328,15 +312,15 @@ void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell)
int width = GetSize(cell->getPort(ID::Y));

for (int idx = 0; idx < GetSize(sel); idx++) {
SigSpec new_data = module->addWire(NEW_ID, GetSize(data) / 2);
SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2);
for (int i = 0; i < GetSize(new_data); i += width) {
for (int k = 0; k < width; k++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, data[i * 2 + k]);
gate->setPort(ID::B, data[i * 2 + width + k]);
gate->setPort(ID::A, data[i*2+k]);
gate->setPort(ID::B, data[i*2+width+k]);
gate->setPort(ID::S, sel[idx]);
gate->setPort(ID::Y, new_data[i + k]);
gate->setPort(ID::Y, new_data[i+k]);
}
}
data = new_data;
Expand All @@ -352,14 +336,14 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
lut_data.extend_u0(1 << cell->getParam(ID::WIDTH).as_int());

for (int idx = 0; GetSize(lut_data) > 1; idx++) {
SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data) / 2);
SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2);
for (int i = 0; i < GetSize(lut_data); i += 2) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, lut_data[i]);
gate->setPort(ID::B, lut_data[i + 1]);
gate->setPort(ID::B, lut_data[i+1]);
gate->setPort(ID::S, lut_ctrl[idx]);
gate->setPort(ID::Y, new_lut_data[i / 2]);
gate->setPort(ID::Y, new_lut_data[i/2]);
}
lut_data = new_lut_data;
}
Expand All @@ -381,11 +365,11 @@ void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
for (int i = 0; i < depth; i++) {
SigSpec in, pat;
for (int j = 0; j < width; j++) {
if (table[2 * i * width + 2 * j + 0] == State::S1) {
if (table[2*i*width + 2*j + 0] == State::S1) {
in.append(ctrl[j]);
pat.append(State::S0);
}
if (table[2 * i * width + 2 * j + 1] == State::S1) {
if (table[2*i*width + 2*j + 1] == State::S1) {
in.append(ctrl[j]);
pat.append(State::S1);
}
Expand Down Expand Up @@ -423,56 +407,56 @@ void simplemap_ff(RTLIL::Module *, RTLIL::Cell *cell)
}
}

void simplemap_get_mappers(dict<IdString, void (*)(RTLIL::Module *, RTLIL::Cell *)> &mappers)
void simplemap_get_mappers(dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
{
mappers[ID($not)] = simplemap_not;
mappers[ID($pos)] = simplemap_pos;
mappers[ID($and)] = simplemap_bitop;
mappers[ID($or)] = simplemap_bitop;
mappers[ID($xor)] = simplemap_bitop;
mappers[ID($xnor)] = simplemap_bitop;
mappers[ID($bweqx)] = simplemap_bitop;
mappers[ID($reduce_and)] = simplemap_reduce;
mappers[ID($reduce_or)] = simplemap_reduce;
mappers[ID($reduce_xor)] = simplemap_reduce;
mappers[ID($not)] = simplemap_not;
mappers[ID($pos)] = simplemap_pos;
mappers[ID($and)] = simplemap_bitop;
mappers[ID($or)] = simplemap_bitop;
mappers[ID($xor)] = simplemap_bitop;
mappers[ID($xnor)] = simplemap_bitop;
mappers[ID($bweqx)] = simplemap_bitop;
mappers[ID($reduce_and)] = simplemap_reduce;
mappers[ID($reduce_or)] = simplemap_reduce;
mappers[ID($reduce_xor)] = simplemap_reduce;
mappers[ID($reduce_xnor)] = simplemap_reduce;
mappers[ID($reduce_bool)] = simplemap_reduce;
mappers[ID($logic_not)] = simplemap_lognot;
mappers[ID($logic_and)] = simplemap_logbin;
mappers[ID($logic_or)] = simplemap_logbin;
mappers[ID($eq)] = simplemap_eqne;
mappers[ID($eqx)] = simplemap_eqne;
mappers[ID($ne)] = simplemap_eqne;
mappers[ID($nex)] = simplemap_eqne;
mappers[ID($mux)] = simplemap_mux;
mappers[ID($bwmux)] = simplemap_bwmux;
mappers[ID($tribuf)] = simplemap_tribuf;
mappers[ID($bmux)] = simplemap_bmux;
mappers[ID($lut)] = simplemap_lut;
mappers[ID($sop)] = simplemap_sop;
mappers[ID($slice)] = simplemap_slice;
mappers[ID($concat)] = simplemap_concat;
mappers[ID($sr)] = simplemap_ff;
mappers[ID($ff)] = simplemap_ff;
mappers[ID($dff)] = simplemap_ff;
mappers[ID($dffe)] = simplemap_ff;
mappers[ID($dffsr)] = simplemap_ff;
mappers[ID($dffsre)] = simplemap_ff;
mappers[ID($adff)] = simplemap_ff;
mappers[ID($sdff)] = simplemap_ff;
mappers[ID($adffe)] = simplemap_ff;
mappers[ID($sdffe)] = simplemap_ff;
mappers[ID($sdffce)] = simplemap_ff;
mappers[ID($aldff)] = simplemap_ff;
mappers[ID($aldffe)] = simplemap_ff;
mappers[ID($dlatch)] = simplemap_ff;
mappers[ID($adlatch)] = simplemap_ff;
mappers[ID($dlatchsr)] = simplemap_ff;
mappers[ID($logic_not)] = simplemap_lognot;
mappers[ID($logic_and)] = simplemap_logbin;
mappers[ID($logic_or)] = simplemap_logbin;
mappers[ID($eq)] = simplemap_eqne;
mappers[ID($eqx)] = simplemap_eqne;
mappers[ID($ne)] = simplemap_eqne;
mappers[ID($nex)] = simplemap_eqne;
mappers[ID($mux)] = simplemap_mux;
mappers[ID($bwmux)] = simplemap_bwmux;
mappers[ID($tribuf)] = simplemap_tribuf;
mappers[ID($bmux)] = simplemap_bmux;
mappers[ID($lut)] = simplemap_lut;
mappers[ID($sop)] = simplemap_sop;
mappers[ID($slice)] = simplemap_slice;
mappers[ID($concat)] = simplemap_concat;
mappers[ID($sr)] = simplemap_ff;
mappers[ID($ff)] = simplemap_ff;
mappers[ID($dff)] = simplemap_ff;
mappers[ID($dffe)] = simplemap_ff;
mappers[ID($dffsr)] = simplemap_ff;
mappers[ID($dffsre)] = simplemap_ff;
mappers[ID($adff)] = simplemap_ff;
mappers[ID($sdff)] = simplemap_ff;
mappers[ID($adffe)] = simplemap_ff;
mappers[ID($sdffe)] = simplemap_ff;
mappers[ID($sdffce)] = simplemap_ff;
mappers[ID($aldff)] = simplemap_ff;
mappers[ID($aldffe)] = simplemap_ff;
mappers[ID($dlatch)] = simplemap_ff;
mappers[ID($adlatch)] = simplemap_ff;
mappers[ID($dlatchsr)] = simplemap_ff;
}

void simplemap(RTLIL::Module *module, RTLIL::Cell *cell)
{
static dict<IdString, void (*)(RTLIL::Module *, RTLIL::Cell *)> mappers;
static dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
static bool initialized_mappers = false;

if (!initialized_mappers) {
Expand All @@ -487,7 +471,7 @@ YOSYS_NAMESPACE_END
PRIVATE_NAMESPACE_BEGIN

struct SimplemapPass : public Pass {
SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") {}
SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
Expand All @@ -509,13 +493,13 @@ struct SimplemapPass : public Pass {
log_header(design, "Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
extra_args(args, 1, design);

dict<IdString, void (*)(RTLIL::Module *, RTLIL::Cell *)> mappers;
dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
simplemap_get_mappers(mappers);

for (auto mod : design->modules()) {
if (!design->selected(mod) || mod->get_blackbox_attribute())
continue;
std::vector<RTLIL::Cell *> cells = mod->cells();
std::vector<RTLIL::Cell*> cells = mod->cells();
for (auto cell : cells) {
if (mappers.count(cell->type) == 0)
continue;
Expand Down
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