proc_prune: do not promote partially redundant assignments. #2458
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Before this commit, in a process like:
process $group_0
assign $o 2'00
attribute \full_case 1
switch \x
case 1'1
assign $o [0] 1'1
case
assign $o [0] 1'0
end
end
"assign $o 2'00" would be promoted to "connect $o [1] 1'0".
Mixing assign and connect statements to different bits of the same
signal results in incorrect codegen from the write_verilog backend.
After this commit, "assign $o 2'00" is pruned to "assign $o [1] 1'0"
as a workaround.
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Thanks for spearheading this! I don't like the idea of this change very much (and I assume neither do you); the coupling of My plan is to review this PR carefully and at the same time decide on the feasibility of a more tractable workaround in |
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Nope, no change in behavior here. This can only be fixed properly on the Verilog backend side, I'm afraid. I have some vague hack ideas for |
According to #2035 (comment), the bug in #2035 requires intrusive changes to write_verilog to be properly fixed.
In the meantime, this PR proposes a workaround to proc_prune to avoid emitting the incriminated corner-case.
The source of the bug would still need to be fixed, but e.g. nMigen users will be able to use proc -nomux without hitting it.