peepopt: Add shiftadd pattern

[phsauter]

This has been lightly discussed in #3873.
Together with #3873 and #3880 it should fix #3833.

Another approach to fix #3833 using attributes is shown in #3875 and #3877.

This transformation has been tested a bit but not completely and never on larger modules. Additionally the benefits to Quality-of-Results are as of now non-obvious and lack empirical evidence (though since #3880 does show benefits and this should allow more of these transformations, QoR should improve).

ToDo:

• Test more synthetic cases for correctness and QoR
• Test effects and correctness on a large module
• Document somewhere

[povik]

I went over it, looks good, dropping the log2scale logic and adding a wraparound check are the only points I consider important.

[phsauter]

I applied most of the suggestions, I may have gone overboard with moving everything to the match-block.

Personally I would leave the log2scale code as I think it isn't too expensive and makes it just a little more versatile, you never know what RTLIL this may encounter.

BTW we could make this work for var signed if we padded the output instead, that is, if inserted a dummy wire on the bottom offset bits
I think this should work? Initially I rejected the possibility of fiddling with the output because of concerns it may increase the number of MUX cells again. Now I realize that this isn't necessary, we can just pad it after the cell so it shouldn't change anything there.

[phsauter]

This new version just passed the yosys tests on ubuntu.

I think its about time to try shiftmul and shiftadd together on pulp-platform/iguana.

[phsauter]

As discussed in the dev-meeting:
I will add the pattern-matching tests for this in a future PR, this one here is considered complete.