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verific: Pass list of top modules to static elaboration #3985

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merged 2 commits into from
Oct 5, 2023
Merged

verific: Pass list of top modules to static elaboration #3985

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23b9e61
verific: Pass list of top modules to static elaboration
jix Oct 5, 2023
47a4b79
verific: Pass top modules to static elaboration when using hierarchy
jix Oct 5, 2023
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225 changes: 133 additions & 92 deletions frontends/verific/verific.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -2495,51 +2495,71 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
for (const auto &i : parameters)
verific_params.Insert(i.first.c_str(), i.second.c_str());

if (top.empty()) {

#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
VerificExtensions::ElaborateAndRewrite("work", &verific_params);
verific_error_msg.clear();
VerificExtensions::ElaborateAndRewrite("work", &verific_params);
verific_error_msg.clear();
#endif

if (top.empty()) {
netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &verific_params);
}
else {
Array veri_modules, vhdl_units;

if (veri_lib) {
VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1);
if (veri_module) {
veri_modules.InsertLast(veri_module);
if (veri_module->IsConfiguration()) {
VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
VeriName *module_name = (VeriName*)cfg->GetTopModuleNames()->GetLast();
VeriLibrary *lib = veri_module->GetLibrary() ;
if (module_name && module_name->IsHierName()) {
VeriName *prefix = module_name->GetPrefix() ;
const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ;

#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--)
#endif
{
Array veri_modules, vhdl_units;

if (veri_lib) {
VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1);
if (veri_module) {
veri_modules.InsertLast(veri_module);
if (veri_module->IsConfiguration()) {
VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
VeriName *module_name = (VeriName*)cfg->GetTopModuleNames()->GetLast();
VeriLibrary *lib = veri_module->GetLibrary() ;
if (module_name && module_name->IsHierName()) {
VeriName *prefix = module_name->GetPrefix() ;
const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ;
}
if (lib && module_name)
top = lib->GetModule(module_name->GetName(), 1)->GetName();
}
if (lib && module_name)
top = lib->GetModule(module_name->GetName(), 1)->GetName();
}
}

// Also elaborate all root modules since they may contain bind statements
MapIter mi;
FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
if (!veri_module->IsRootModule()) continue;
veri_modules.InsertLast(veri_module);
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
if (!static_elaborate)
#endif
{
// Also elaborate all root modules since they may contain bind statements
MapIter mi;
FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
if (!veri_module->IsRootModule()) continue;
veri_modules.InsertLast(veri_module);
}
}
}
}

#ifdef VERIFIC_VHDL_SUPPORT
if (vhdl_lib) {
VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(top.c_str());
if (vhdl_unit)
vhdl_units.InsertLast(vhdl_unit);
}
if (vhdl_lib) {
VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(top.c_str());
if (vhdl_unit)
vhdl_units.InsertLast(vhdl_unit);
}
#endif

#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
if (static_elaborate) {
VerificExtensions::ElaborateAndRewrite("work", &veri_modules, &vhdl_units, &verific_params);
verific_error_msg.clear();
continue;
}
#endif
netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params);

netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params);
}
}

Netlist *nl;
Expand Down Expand Up @@ -3595,15 +3615,16 @@ struct VerificPass : public Pass {

std::set<std::string> top_mod_names;

if (mode_all)
{

#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
VerificExtensions::ElaborateAndRewrite(work, &parameters);
verific_error_msg.clear();
VerificExtensions::ElaborateAndRewrite(work, &parameters);
verific_error_msg.clear();
#endif
if (!ppfile.empty())
veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str());
if (!ppfile.empty())
veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str());

if (mode_all)
{
log("Running hier_tree::ElaborateAll().\n");

VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1);
Expand All @@ -3628,73 +3649,93 @@ struct VerificPass : public Pass {
if (argidx == GetSize(args))
cmd_error(args, argidx, "No top module specified.\n");

VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1);
Array *netlists = nullptr;

#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--)
#endif
{

VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1);
#ifdef VERIFIC_VHDL_SUPPORT
VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
#endif

Array veri_modules, vhdl_units;
for (; argidx < GetSize(args); argidx++)
{
const char *name = args[argidx].c_str();
top_mod_names.insert(name);

VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr;
if (veri_module) {
if (veri_module->IsConfiguration()) {
log("Adding Verilog configuration '%s' to elaboration queue.\n", name);
veri_modules.InsertLast(veri_module);

top_mod_names.erase(name);

VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
VeriName *module_name;
int i;
FOREACH_ARRAY_ITEM(cfg->GetTopModuleNames(), i, module_name) {
VeriLibrary *lib = veri_module->GetLibrary() ;
if (module_name && module_name->IsHierName()) {
VeriName *prefix = module_name->GetPrefix() ;
const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
if (work != lib_name) lib = veri_file::GetLibrary(lib_name, 1) ;
Array veri_modules, vhdl_units;
for (int i = argidx; i < GetSize(args); i++)
{
const char *name = args[i].c_str();
top_mod_names.insert(name);

VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr;
if (veri_module) {
if (veri_module->IsConfiguration()) {
log("Adding Verilog configuration '%s' to elaboration queue.\n", name);
veri_modules.InsertLast(veri_module);

top_mod_names.erase(name);

VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
VeriName *module_name;
int i;
FOREACH_ARRAY_ITEM(cfg->GetTopModuleNames(), i, module_name) {
VeriLibrary *lib = veri_module->GetLibrary() ;
if (module_name && module_name->IsHierName()) {
VeriName *prefix = module_name->GetPrefix() ;
const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
if (work != lib_name) lib = veri_file::GetLibrary(lib_name, 1) ;
}
if (lib && module_name)
top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName());
}
if (lib && module_name)
top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName());
} else {
log("Adding Verilog module '%s' to elaboration queue.\n", name);
veri_modules.InsertLast(veri_module);
}
} else {
log("Adding Verilog module '%s' to elaboration queue.\n", name);
veri_modules.InsertLast(veri_module);
continue;
}
continue;
}
#ifdef VERIFIC_VHDL_SUPPORT
VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr;
if (vhdl_unit) {
log("Adding VHDL unit '%s' to elaboration queue.\n", name);
vhdl_units.InsertLast(vhdl_unit);
continue;
}
VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr;
if (vhdl_unit) {
log("Adding VHDL unit '%s' to elaboration queue.\n", name);
vhdl_units.InsertLast(vhdl_unit);
continue;
}
#endif
log_error("Can't find module/unit '%s'.\n", name);
}
log_error("Can't find module/unit '%s'.\n", name);
}

#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
if (static_elaborate) {
VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, &parameters);
verific_error_msg.clear();
#endif
if (!ppfile.empty())
veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str());

const char *lib_name = nullptr;
SetIter si;
FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) {
VeriLibrary* veri_lib = veri_file::GetLibrary(lib_name, 0);
if (veri_lib) {
// Also elaborate all root modules since they may contain bind statements
MapIter mi;
VeriModule *veri_module;
FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
if (!veri_module->IsRootModule()) continue;
veri_modules.InsertLast(veri_module);
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
continue;
}
#endif
const char *lib_name = nullptr;
SetIter si;
FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) {
VeriLibrary* veri_lib = veri_file::GetLibrary(lib_name, 0);
if (veri_lib) {
// Also elaborate all root modules since they may contain bind statements
MapIter mi;
VeriModule *veri_module;
FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
if (!veri_module->IsRootModule()) continue;
veri_modules.InsertLast(veri_module);
}
}
}

log("Running hier_tree::Elaborate().\n");
netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &parameters);
}

log("Running hier_tree::Elaborate().\n");
Array *netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &parameters);
Netlist *nl;
int i;

Expand Down
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