write_verilog: avoid emitting empty cases. #3992
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The Verilog grammar does not allow an empty case. Most synthesis tools are quite permissive about this, but Quartus is not. This causes problems for amaranth with Quartus (see amaranth-lang/amaranth#931).
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Can confirm this fixed amaranth-lang/amaranth#931 (the compile error at least) (EDIT: it fixed it completely) |
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The Verilog grammar does not allow an empty case. Most synthesis tools are quite permissive about this, but Quartus is not. This causes problems for amaranth with Quartus (see amaranth-lang/amaranth#931).