lattice: Fix mapping onto DP8KC for data width 1 or 2 #4087
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mmicko
approved these changes
Dec 21, 2023
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This appears to be the right wiring of
DP8KCper the MachXO3 simulation model I have at hand.Some points:
I don't know if this applies to all
DP8KCprimitives across the Lattice families.Reading into the simulation model, it seems one cannot map a memory with write port of width 18 and read port of width 2 onto
DP8KC. This is becauseDIB1, which would be used for the 10th data bit input, gets ignored. If this is true, or even if it's just a bug of the simulation model, we may want to disable this configuration in libmap inference of$__PDPW8KC_. UPDATE: done in the second commit