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connect: Do interpret selection arguments #4177

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Feb 19, 2024
+15 −14
Merged

connect: Do interpret selection arguments #4177

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29 changes: 15 additions & 14 deletions passes/cmds/connect.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -47,20 +47,20 @@ struct ConnectPass : public Pass {
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" connect [-nomap] [-nounset] -set <lhs-expr> <rhs-expr>\n");
log(" connect [-nomap] [-nounset] -set <lhs-expr> <rhs-expr> [selection]\n");
log("\n");
log("Create a connection. This is equivalent to adding the statement 'assign\n");
log("<lhs-expr> = <rhs-expr>;' to the Verilog input. Per default, all existing\n");
log("drivers for <lhs-expr> are unconnected. This can be overwritten by using\n");
log("the -nounset option.\n");
log("\n");
log("\n");
log(" connect [-nomap] -unset <expr>\n");
log(" connect [-nomap] -unset <expr> [selection]\n");
log("\n");
log("Unconnect all existing drivers for the specified expression.\n");
log("\n");
log("\n");
log(" connect [-nomap] [-assert] -port <cell> <port> <expr>\n");
log(" connect [-nomap] [-assert] -port <cell> <port> <expr> [selection]\n");
log("\n");
log("Connect the specified cell port to the specified cell port.\n");
log("\n");
Expand All @@ -80,17 +80,6 @@ struct ConnectPass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
RTLIL::Module *module = nullptr;
for (auto mod : design->selected_modules()) {
if (module != nullptr)
log_cmd_error("Multiple modules selected: %s, %s\n", log_id(module->name), log_id(mod->name));
module = mod;
}
if (module == nullptr)
log_cmd_error("No modules selected.\n");
if (!module->processes.empty())
log_cmd_error("Found processes in selected module.\n");

bool flag_nounset = false, flag_nomap = false, flag_assert = false;
std::string set_lhs, set_rhs, unset_expr;
std::string port_cell, port_port, port_expr;
Expand Down Expand Up @@ -128,6 +117,18 @@ struct ConnectPass : public Pass {
}
break;
}
extra_args(args, argidx, design);

RTLIL::Module *module = nullptr;
for (auto mod : design->selected_modules()) {
if (module != nullptr)
log_cmd_error("Multiple modules selected: %s, %s\n", log_id(module->name), log_id(mod->name));
module = mod;
}
if (module == nullptr)
log_cmd_error("No modules selected.\n");
if (!module->processes.empty())
log_cmd_error("Found processes in selected module.\n");

SigMap sigmap;
if (!flag_nomap)
Expand Down
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