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ci: Fix CXXSTD typo #4181

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merged 4 commits into from
Feb 8, 2024
Merged

ci: Fix CXXSTD typo #4181

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3f457f2
ci: Fix CXXSTD typo
povik Feb 4, 2024
97b8ee5
ci: Get a dump of yosys-config into the build log
povik Feb 4, 2024
0cdd427
ci: ignore yosys-config return code
KrystalDelusion Feb 5, 2024
af1a5cf
Address `SigBit`/`SigSpec` confusion issues under c++20
povik Feb 8, 2024
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6 changes: 5 additions & 1 deletion .github/workflows/test-linux.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -111,10 +111,14 @@ jobs:
shell: bash
run: |
make config-${CC%%-*}
make -j${{ env.procs }} CCXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
make -j${{ env.procs }} CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC

- name: Run tests
if: (matrix.cpp_std == 'c++11') && (matrix.compiler == 'gcc-11')
shell: bash
run: |
make -j${{ env.procs }} test CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC

- name: Log yosys-config output
run: |
./yosys-config || true
2 changes: 1 addition & 1 deletion passes/opt/opt_dff.cc
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Expand Up @@ -353,7 +353,7 @@ struct OptDffWorker
// Try a more complex conversion to plain async reset.
State val_neutral = ff.pol_set ? State::S0 : State::S1;
Const val_arst;
SigSpec sig_arst;
SigBit sig_arst;
if (ff.sig_clr[0] == val_neutral)
sig_arst = ff.sig_set[0];
else
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3 changes: 2 additions & 1 deletion passes/opt/opt_ffinv.cc
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Expand Up @@ -38,6 +38,7 @@ struct OptFfInvWorker
// - ... which has no other users
// - all users of FF are LUTs
bool push_d_inv(FfData &ff) {
log_assert(ff.width == 1);
if (index.query_is_input(ff.sig_d))
return false;
if (index.query_is_output(ff.sig_d))
Expand Down Expand Up @@ -90,7 +91,7 @@ struct OptFfInvWorker
int flip_mask = 0;
SigSpec sig_a = lut->getPort(ID::A);
for (int i = 0; i < GetSize(sig_a); i++) {
if (index.sigmap(sig_a[i]) == index.sigmap(ff.sig_q)) {
if (index.sigmap(sig_a[i]) == index.sigmap(ff.sig_q[0])) {
flip_mask |= 1 << i;
}
}
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8 changes: 6 additions & 2 deletions passes/opt/opt_lut.cc
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Expand Up @@ -167,7 +167,11 @@ struct OptLutWorker
legal = false;
break;
}
if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic.second->getPort(dlogic_conn.second)))

if (lut_dlogic.second->getPort(dlogic_conn.second).size() != 1)
continue;

if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic.second->getPort(dlogic_conn.second)[0]))
{
log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second));
log_debug(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic.second->type.c_str(), dlogic_conn.second.c_str(), log_signal(lut_dlogic.second->getPort(dlogic_conn.second)));
Expand Down Expand Up @@ -314,7 +318,7 @@ struct OptLutWorker

auto lutA = worklist.pop();
SigSpec lutA_input = sigmap(lutA->getPort(ID::A));
SigSpec lutA_output = sigmap(lutA->getPort(ID::Y)[0]);
SigBit lutA_output = sigmap(lutA->getPort(ID::Y)[0]);
int lutA_width = lutA->getParam(ID::WIDTH).as_int();
int lutA_arity = luts_arity[lutA];
pool<int> &lutA_dlogic_inputs = luts_dlogic_inputs[lutA];
Expand Down
4 changes: 2 additions & 2 deletions passes/pmgen/ice40_dsp.pmg
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Expand Up @@ -346,7 +346,7 @@ endmatch
code argQ argD
{
if (clock != SigBit()) {
if (port(ff, \CLK) != clock)
if (port(ff, \CLK)[0] != clock)
reject;
if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
reject;
Expand Down Expand Up @@ -393,7 +393,7 @@ endmatch
code argQ
if (ff) {
if (clock != SigBit()) {
if (port(ff, \CLK) != clock)
if (port(ff, \CLK)[0] != clock)
reject;
if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
reject;
Expand Down
4 changes: 2 additions & 2 deletions passes/pmgen/xilinx_dsp.pmg
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Expand Up @@ -415,7 +415,7 @@ match ff
filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ

filter clock == SigBit() || port(ff, \CLK) == clock
filter clock == SigBit() || port(ff, \CLK)[0] == clock
endmatch

code argQ
Expand Down Expand Up @@ -465,7 +465,7 @@ match ff
filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
filter port(ff, \D).extract(offset, GetSize(argD)) == argD

filter clock == SigBit() || port(ff, \CLK) == clock
filter clock == SigBit() || port(ff, \CLK)[0] == clock
endmatch

code argQ
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4 changes: 2 additions & 2 deletions passes/pmgen/xilinx_dsp48a.pmg
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Expand Up @@ -354,7 +354,7 @@ match ff
filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ

filter clock == SigBit() || port(ff, \CLK) == clock
filter clock == SigBit() || port(ff, \CLK)[0] == clock
endmatch

code argQ
Expand Down Expand Up @@ -404,7 +404,7 @@ match ff
filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
filter port(ff, \D).extract(offset, GetSize(argD)) == argD

filter clock == SigBit() || port(ff, \CLK) == clock
filter clock == SigBit() || port(ff, \CLK)[0] == clock
endmatch

code argQ
Expand Down
2 changes: 1 addition & 1 deletion passes/pmgen/xilinx_dsp_CREG.pmg
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Expand Up @@ -135,7 +135,7 @@ match ff
filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ

filter clock == SigBit() || port(ff, \CLK) == clock
filter clock == SigBit() || port(ff, \CLK)[0] == clock
endmatch

code argQ
Expand Down
4 changes: 2 additions & 2 deletions passes/pmgen/xilinx_dsp_cascade.pmg
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Expand Up @@ -46,7 +46,7 @@ pattern xilinx_dsp_cascade
udata <std::function<SigSpec(const SigSpec&)>> unextend
udata <vector<std::tuple<Cell*,int,int,int>>> chain longest_chain
state <Cell*> next
state <SigSpec> clock
state <SigBit> clock
state <int> AREG BREG

// Variables used for subpatterns
Expand Down Expand Up @@ -395,7 +395,7 @@ match ff
filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ

filter clock == SigBit() || port(ff, \CLK) == clock
filter clock == SigBit() || port(ff, \CLK)[0] == clock
endmatch

code argQ
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2 changes: 1 addition & 1 deletion passes/techmap/extract_fa.cc
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Expand Up @@ -281,7 +281,7 @@ struct ExtractFaWorker
void assign_new_driver(SigBit bit, SigBit new_driver)
{
Cell *cell = driver.at(bit);
if (sigmap(cell->getPort(ID::Y)) == bit) {
if (sigmap(cell->getPort(ID::Y)) == SigSpec(bit)) {
cell->setPort(ID::Y, module->addWire(NEW_ID));
module->connect(bit, new_driver);
}
Expand Down
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