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abc9: Experiment with importing structural choices #4283

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@povik povik commented Mar 15, 2024

This is a bit of code on top of #4282 to have the structural choices that abc9 comes up reimported back into Yosys, for inspection and possibly other uses.

Minimal example where one sees it in action:

read_verilog <<EOF
(* top *)
module top(a, b, y);
	input wire [1:0] a;
	input wire [1:0] b;
	output wire [1:0] y;
	assign y = a * b;
endmodule
EOF
opt_clean
techmap
splitnets -ports
abc9 -script +&synch2;,&ps;;
show

graph

povik added 7 commits March 14, 2024 22:11
Formerly when you didn't pass any options to `abc9` it would source a
LUT library from the current design by considering any module with an
`abc9_lut` attribute to be an available mapping primitive.

Make the change to condition this behavior on a `-lutlib` option, and
instead make `abc9` without any options perform a non-mapping mode in
which the netlist is reimported back into Yosys as an and-inverter
graph.
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povik commented Apr 29, 2024

Let me leave a note that the imported $__choice nodes represent equivalences up to a negation. (One can find out the value of the referenced nodes under all PIs being zero to recover polarities.)

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