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extract: add arbitrary port width matching #4304

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phsauter
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The goal is to improve extract and make it easier to use in scenarios similar to the ones described in the extract example.

The final goal is to extract something like a multiplier followed by an arbitrary amount of variable-width adders.

ToDo:

  • minimum port widths per port (in user port matching)
  • avoid expanding ports to max width with 'Z
  • document in macc examples

- use minimum port width from solver
- copy over WIDTH and SIGNED parameters to new cell
@@ -427,6 +438,10 @@ struct ExtractPass : public Pass {
log(" -mine_max_fanout <num>\n");
log(" don't consider internal signals with more than <num> connections\n");
log("\n");
log(" -min_port_width <num>\n");
log(" match all subcircuits with port-sizes between needle port widths and this number\n");
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So "this number" is lower than the needle port widths?

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Yes, this number defines the lower bounds of the needle port width (it applies to all ports).
Usually the port widths must match exactly, this exposes an existing feature of the algorithm.
So: hay_port_width ∈ [min_width; needle_port_width]

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Yes, I am asking due to the phrasing, which suggested to me <num> is an upper bound, not a lower bound. Not sure what we should change it to though.

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maybe something like:

match all subcircuits with port widths from <num> up to the needle port width given in the map.

This does not yet seem to work completely as intended.
The idea is to trim the port widths of the extracted circuits,
so that it does not leave X bits as padding at the MSBs.
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