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verific: expose library name as module attribute #4339

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merged 1 commit into from
Apr 15, 2024
Merged

verific: expose library name as module attribute #4339

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1 change: 1 addition & 0 deletions frontends/verific/verific.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -1430,6 +1430,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
}
import_attributes(module->attributes, nl, nl);
module->set_string_attribute(ID::hdlname, nl->CellBaseName());
module->set_string_attribute(ID(library), nl->Owner()->Owner()->Name());
#ifdef VERIFIC_VHDL_SUPPORT
if (nl->IsFromVhdl()) {
NameSpace name_space(0);
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