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Dark theme images for docs #4391

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May 13, 2024
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Dark theme images for docs #4391

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9be7089
Docs-css: Add invert-helper class for images
KrystalDelusion May 10, 2024
3a36612
Docs: Apply invert-helper where needed
KrystalDelusion May 10, 2024
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14 changes: 14 additions & 0 deletions docs/source/_static/yosyshq.css
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Expand Up @@ -24,3 +24,17 @@ a.external {
th {
text-align: left;
}

body[data-theme="dark"] {
.invert-helper {
filter: url("data:image/svg+xml,<svg xmlns='http%3A//www.w3.org/2000/svg'><filter id='f'><feColorMatrix color-interpolation-filters='sRGB' type='matrix' values='1.47 -1.73 -0.467 0 0.867 -0.733 0.467 -0.467 0 0.867 -0.667 -1.07 1.07 0 0.867 0 0 0 1.0 0'></feColorMatrix></filter></svg>#f");
}
}

@media (prefers-color-scheme: dark) {
body:not([data-theme="light"]) {
.invert-helper {
filter: url("data:image/svg+xml,<svg xmlns='http%3A//www.w3.org/2000/svg'><filter id='f'><feColorMatrix color-interpolation-filters='sRGB' type='matrix' values='1.47 -1.73 -0.467 0 0.867 -0.733 0.467 -0.467 0 0.867 -0.667 -1.07 1.07 0 0.867 0 0 0 1.0 0'></feColorMatrix></filter></svg>#f");
}
}
}
8 changes: 4 additions & 4 deletions docs/source/appendix/primer.rst
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Expand Up @@ -24,7 +24,7 @@ circuit to a functionally equivalent low-level representation of a circuit.
abstraction and how they relate to different kinds of synthesis.

.. figure:: /_images/primer/basics_abstractions.*
:class: width-helper
:class: width-helper invert-helper
:name: fig:Basics_abstractions

Different levels of abstraction and synthesis.
Expand Down Expand Up @@ -499,7 +499,7 @@ using a series of tools and the results are again verified using simulation.
This process is illustrated in :numref:`Fig. %s <fig:Basics_flow>`.

.. figure:: /_images/primer/basics_flow.*
:class: width-helper
:class: width-helper invert-helper
:name: fig:Basics_flow

Typical design flow. Green boxes represent manually created models.
Expand Down Expand Up @@ -598,7 +598,7 @@ Let's consider the following BNF (in Bison syntax):
expr: TOK_IDENTIFIER | TOK_NUMBER | expr TOK_PLUS expr;

.. figure:: /_images/primer/basics_parsetree.*
:class: width-helper
:class: width-helper invert-helper
:name: fig:Basics_parsetree

Example parse tree for the Verilog expression
Expand Down Expand Up @@ -627,7 +627,7 @@ suitable for further processing. In compilers this is often an assembler-like
three-address-code intermediate representation. :cite:p:`Dragonbook`

.. figure:: /_images/primer/basics_ast.*
:class: width-helper
:class: width-helper invert-helper
:name: fig:Basics_ast

Example abstract syntax tree for the Verilog expression
Expand Down
32 changes: 16 additions & 16 deletions docs/source/getting_started/example_synth.rst
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Expand Up @@ -122,7 +122,7 @@ Since we're just getting started, let's instead begin with :yoscrypt:`hierarchy
Our ``addr_gen`` circuit now looks like this:

.. figure:: /_images/code_examples/fifo/addr_gen_hier.*
:class: width-helper
:class: width-helper invert-helper
:name: addr_gen_hier

``addr_gen`` module after :cmd:ref:`hierarchy`
Expand All @@ -145,7 +145,7 @@ we run it. For now, we will call :yoscrypt:`proc -noopt` to prevent some
automatic optimizations which would normally happen.

.. figure:: /_images/code_examples/fifo/addr_gen_proc.*
:class: width-helper
:class: width-helper invert-helper
:name: addr_gen_proc

``addr_gen`` module after :yoscrypt:`proc -noopt`
Expand All @@ -166,7 +166,7 @@ the same time by separating them with a colon and space: :yoscrypt:`opt_expr;
clean`.

.. figure:: /_images/code_examples/fifo/addr_gen_clean.*
:class: width-helper
:class: width-helper invert-helper
:name: addr_gen_clean

``addr_gen`` module after :yoscrypt:`opt_expr; clean`
Expand Down Expand Up @@ -252,7 +252,7 @@ command only works with a single module, so you may need to call it with
:doc:`/getting_started/scripting_intro` has more on how to use :cmd:ref:`show`.

.. figure:: /_images/code_examples/fifo/rdata_proc.*
:class: width-helper
:class: width-helper invert-helper
:name: rdata_proc

``rdata`` output after :cmd:ref:`proc`
Expand Down Expand Up @@ -298,7 +298,7 @@ optimizations between modules which would otherwise be missed. Let's run
:caption: output of :yoscrypt:`flatten;;`

.. figure:: /_images/code_examples/fifo/rdata_flat.*
:class: width-helper
:class: width-helper invert-helper
:name: rdata_flat

``rdata`` output after :yoscrypt:`flatten;;`
Expand Down Expand Up @@ -385,7 +385,7 @@ options is able to fold one of the ``$mux`` cells into the ``$adff`` to form an
:caption: output of :cmd:ref:`opt_dff`

.. figure:: /_images/code_examples/fifo/rdata_adffe.*
:class: width-helper
:class: width-helper invert-helper
:name: rdata_adffe

``rdata`` output after :cmd:ref:`opt_dff`
Expand Down Expand Up @@ -424,7 +424,7 @@ the schematic and see the output of that cell has now changed.
.. todo:: pending bugfix in :cmd:ref:`wreduce` and/or :cmd:ref:`opt_clean`

.. figure:: /_images/code_examples/fifo/rdata_wreduce.*
:class: width-helper
:class: width-helper invert-helper
:name: rdata_wreduce

``rdata`` output after :cmd:ref:`wreduce`
Expand All @@ -446,7 +446,7 @@ Our next command to run is
:caption: output of :cmd:ref:`memory_dff`

.. figure:: /_images/code_examples/fifo/rdata_memrdv2.*
:class: width-helper
:class: width-helper invert-helper
:name: rdata_memrdv2

``rdata`` output after :cmd:ref:`memory_dff`
Expand Down Expand Up @@ -535,7 +535,7 @@ example design:
:caption: output of :cmd:ref:`alumacc`

.. figure:: /_images/code_examples/fifo/rdata_alumacc.*
:class: width-helper
:class: width-helper invert-helper
:name: rdata_alumacc

``rdata`` output after :cmd:ref:`alumacc`
Expand All @@ -553,7 +553,7 @@ operating on the same memory only in the abstract. :cmd:ref:`memory_collect`
combines all of the reads and writes for a memory block into a single cell.

.. figure:: /_images/code_examples/fifo/rdata_coarse.*
:class: width-helper
:class: width-helper invert-helper
:name: rdata_coarse

``rdata`` output after :cmd:ref:`memory_collect`
Expand Down Expand Up @@ -604,7 +604,7 @@ Mapping to hard memory blocks uses a combination of :cmd:ref:`memory_libmap` and
:caption: ``map_ram`` section

.. figure:: /_images/code_examples/fifo/rdata_map_ram.*
:class: width-helper
:class: width-helper invert-helper
:name: rdata_map_ram

``rdata`` output after :ref:`map_ram`
Expand Down Expand Up @@ -646,7 +646,7 @@ into flip flops (the ``logic fallback``) with :cmd:ref:`memory_map`.
:caption: ``map_ffram`` section

.. figure:: /_images/code_examples/fifo/rdata_map_ffram.*
:class: width-helper
:class: width-helper invert-helper
:name: rdata_map_ffram

``rdata`` output after :ref:`map_ffram`
Expand Down Expand Up @@ -682,7 +682,7 @@ replaced with single-bit ``$_MUX_`` and ``$_DFFE_PP0P_`` cells, while the
:caption: ``map_gates`` section

.. figure:: /_images/code_examples/fifo/rdata_map_gates.*
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:class: width-helper invert-helper
:name: rdata_map_gates

``rdata`` output after :ref:`map_gates`
Expand Down Expand Up @@ -711,7 +711,7 @@ instead with an ``$_AND_`` cell.
:caption: ``map_ffs`` section

.. figure:: /_images/code_examples/fifo/rdata_map_ffs.*
:class: width-helper
:class: width-helper invert-helper
:name: rdata_map_ffs

``rdata`` output after :ref:`map_ffs`
Expand All @@ -737,7 +737,7 @@ what the difference between these two commands are, refer to
:caption: ``map_luts`` section

.. figure:: /_images/code_examples/fifo/rdata_map_luts.*
:class: width-helper
:class: width-helper invert-helper
:name: rdata_map_luts

``rdata`` output after :ref:`map_luts`
Expand All @@ -754,7 +754,7 @@ Finally we use :cmd:ref:`techmap` to map the generic ``$lut`` cells to iCE40
:caption: ``map_cells`` section

.. figure:: /_images/code_examples/fifo/rdata_map_cells.*
:class: width-helper
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:name: rdata_map_cells

``rdata`` output after :ref:`map_cells`
Expand Down
6 changes: 3 additions & 3 deletions docs/source/getting_started/scripting_intro.rst
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Expand Up @@ -108,7 +108,7 @@ what the different symbols represent, see :ref:`interactive_show` and the
:doc:`/using_yosys/more_scripting/interactive_investigation` page.

.. figure:: /_images/code_examples/fifo/addr_gen_show.*
:class: width-helper
:class: width-helper invert-helper
:name: addr_gen_show

Calling :yoscrypt:`show addr_gen` after :cmd:ref:`hierarchy`
Expand Down Expand Up @@ -158,7 +158,7 @@ selection<select_new_cells>` and called it ``new_cells``? We saw in the
``$eq``. We can call :cmd:ref:`show` on that selection just as easily:

.. figure:: /_images/code_examples/fifo/new_cells_show.*
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:name: new_cells_show

Calling :yoscrypt:`show -notitle @new_cells`
Expand All @@ -173,7 +173,7 @@ the two ``PROC`` blocks. To achieve this highlight, we make use of the
:yoscrypt:`-color` option:

.. figure:: /_images/code_examples/fifo/addr_gen_hier.*
:class: width-helper
:class: width-helper invert-helper

Calling :yoscrypt:`show -color maroon3 @new_cells -color cornflowerblue p:* -notitle`

Expand Down
2 changes: 1 addition & 1 deletion docs/source/introduction.rst
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Expand Up @@ -151,7 +151,7 @@ extensible and therefore is a good basis for implementing custom synthesis tools
for specialised tasks.

.. figure:: /_images/primer/levels_of_abstraction.*
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:name: fig:Levels_of_abstraction

Where Yosys exists in the layers of abstraction
Expand Down
24 changes: 12 additions & 12 deletions docs/source/using_yosys/more_scripting/interactive_investigation.rst
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Expand Up @@ -56,7 +56,7 @@ is shown.
``xdot example_first.dot`` etc.

.. figure:: /_images/code_examples/show/example_first.*
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Output of the first :cmd:ref:`show` command in :numref:`example_ys`

Expand Down Expand Up @@ -88,7 +88,7 @@ The :cmd:ref:`proc` command transforms the process from the first diagram into a
multiplexer and a d-type flip-flop, which brings us to the second diagram:

.. figure:: /_images/code_examples/show/example_second.*
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Output of the second :cmd:ref:`show` command in :numref:`example_ys`

Expand All @@ -110,7 +110,7 @@ In this script we directly call :cmd:ref:`opt` as the next step, which finally
leads us to the third diagram:

.. figure:: /_images/code_examples/show/example_third.*
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:name: example_out

Output of the third :cmd:ref:`show` command in :ref:`example_ys`
Expand All @@ -137,7 +137,7 @@ that operate on wide integers, it also introduces some additional complexity
when the individual bits of of a signal vector are accessed.

.. figure:: /_images/code_examples/show/splice.*
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:class: width-helper invert-helper
:name: splice_dia

Output of ``yosys -p 'prep -top splice_demo; show' splice.v``
Expand Down Expand Up @@ -165,7 +165,7 @@ Gate level netlists
mapped to a cell library:

.. figure:: /_images/code_examples/show/cmos_00.*
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:name: first_pitfall

A half-adder built from simple CMOS gates, demonstrating common pitfalls when
Expand All @@ -185,7 +185,7 @@ column. Secondly the two-bit vector ``y`` requires breakout-boxes for its
individual bits, resulting in an unnecessary complex diagram.

.. figure:: /_images/code_examples/show/cmos_01.*
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:class: width-helper invert-helper
:name: second_pitfall

Effects of :cmd:ref:`splitnets` command and of providing a cell library on
Expand Down Expand Up @@ -358,10 +358,10 @@ reorganizing a module in Yosys and checking the resulting circuit.
:end-before: cd ..

.. figure:: /_images/code_examples/scrambler/scrambler_p01.*
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:class: width-helper invert-helper

.. figure:: /_images/code_examples/scrambler/scrambler_p02.*
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Analyzing the resulting circuit with :doc:`/cmd/eval`:

Expand Down Expand Up @@ -442,7 +442,7 @@ if the circuit under investigation is encapsulated in a separate module.
Recall the ``memdemo`` design from :ref:`advanced_logic_cones`:

.. figure:: /_images/code_examples/selections/memdemo_00.*
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``memdemo``

Expand All @@ -463,18 +463,18 @@ name of the new cell in the current module. The resulting circuits are shown
below.

.. figure:: /_images/code_examples/selections/submod_02.*
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``outstage``

.. figure:: /_images/code_examples/selections/submod_03.*
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:name: selstage

``selstage``

.. figure:: /_images/code_examples/selections/submod_01.*
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``scramble``

Expand Down
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