Redo internal cell memory layout

.gitmodules

@@ -1,3 +1,6 @@
 [submodule "abc"]
 	path = abc
 	url = https://github.com/YosysHQ/abc
+[submodule "tracy"]
+	path = tracy
+	url = [email protected]:wolfpld/tracy.git

Makefile

@@ -45,10 +45,10 @@ DISABLE_SPAWN := 0
 DISABLE_ABC_THREADS := 0
 
 # clang sanitizers
-SANITIZER =
+# SANITIZER =
 # SANITIZER = address
 # SANITIZER = memory
-# SANITIZER = undefined
+SANITIZER = undefined
 # SANITIZER = cfi
 
 PROGRAM_PREFIX :=
@@ -90,8 +90,8 @@ all: top-all
 YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST)))
 VPATH := $(YOSYS_SRC)
 
-CXXSTD ?= c++11
-CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include
+CXXSTD ?= c++17
+CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -Itracy/public -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include
 LIBS := $(LIBS) -lstdc++ -lm
 PLUGIN_LINKFLAGS :=
 PLUGIN_LIBS :=
@@ -227,6 +227,15 @@ LINKFLAGS += -flto
 endif
 endif
 
+ifneq ($(PROFILER),)
+$(info [Profiler] $(PROFILER))
+CXXFLAGS += -g -fno-omit-frame-pointer -fno-optimize-sibling-calls
+LINKFLAGS += -g
+ifneq ($(findstring tracy,$(PROFILER)),)
+CXXFLAGS += -DTRACY_ENABLE
+endif
+endif
+
 else ifeq ($(CONFIG),gcc)
 CXX = g++
 CXXFLAGS += -std=$(CXXSTD) -Os
@@ -557,6 +566,7 @@ $(eval $(call add_include_file,kernel/celledges.h))
 $(eval $(call add_include_file,kernel/celltypes.h))
 $(eval $(call add_include_file,kernel/consteval.h))
 $(eval $(call add_include_file,kernel/constids.inc))
+$(eval $(call add_include_file,kernel/compat.h))
 $(eval $(call add_include_file,kernel/cost.h))
 $(eval $(call add_include_file,kernel/ff.h))
 $(eval $(call add_include_file,kernel/ffinit.h))
@@ -595,7 +605,9 @@ $(eval $(call add_include_file,frontends/ast/ast_binding.h))
 $(eval $(call add_include_file,frontends/blif/blifparse.h))
 $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h))
 
-OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o
+# See -DTRACY_ENABLE
+OBJS += tracy/public/TracyClient.o
+OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/adds.shim.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/compat.o
 OBJS += kernel/binding.o
 OBJS += kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o
 ifeq ($(ENABLE_ZLIB),1)

backends/blif/blif.cc

@@ -141,9 +141,10 @@ struct BlifDumper
 		return "subckt";
 	}
 
-	void dump_params(const char *command, dict<IdString, Const> &params)
+	template <typename SmellsLikeDict>
+	void dump_params(const char *command, SmellsLikeDict &params)
 	{
-		for (auto &param : params) {
+		for (auto param : params) {
 			f << stringf("%s %s ", command, log_id(param.first));
 			if (param.second.flags & RTLIL::CONST_FLAG_STRING) {
 				std::string str = param.second.decode_string();

backends/cxxrtl/cxxrtl_backend.cc

@@ -2326,7 +2326,8 @@ struct CxxrtlWorker {
 		f << escape_c_string(data);
 	}
 
-	void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map) {
+	template <typename SmellsLikeDict>
+	void dump_metadata_map(const SmellsLikeDict &metadata_map) {
 		if (metadata_map.empty()) {
 			f << "metadata_map()";
 		} else {

backends/edif/edif.cc

@@ -473,7 +473,7 @@ struct EdifBackend : public Backend {
 				*f << stringf("          (instance %s\n", EDIF_DEF(cell->name));
 				*f << stringf("            (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
 						lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
-				for (auto &p : cell->parameters)
+				for (auto p : cell->parameters)
 					add_prop(p.first, p.second);
 				if (attr_properties)
 					for (auto &p : cell->attributes)

backends/firrtl/firrtl.cc

@@ -480,32 +480,32 @@ struct FirrtlWorker
 		wire_exprs.push_back(stringf("%s" "inst %s%s of %s %s", indent.c_str(), cell_name.c_str(), cell_name_comment.c_str(), instanceName.c_str(), cellFileinfo.c_str()));
 
 		for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) {
-			if (it->second.size() > 0) {
-				const SigSpec &secondSig = it->second;
-				const std::string firstName = cell_name + "." + make_id(it->first);
+			if ((*it).second.size() > 0) {
+				const SigSpec &secondSig = (*it).second;
+				const std::string firstName = cell_name + "." + make_id((*it).first);
 				const std::string secondExpr = make_expr(secondSig);
 				// Find the direction for this port.
-				FDirection dir = getPortFDirection(it->first, instModule);
+				FDirection dir = getPortFDirection((*it).first, instModule);
 				std::string sourceExpr, sinkExpr;
 				const SigSpec *sinkSig = nullptr;
 				switch (dir) {
 					case FD_INOUT:
-						log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", cell_type.c_str(), log_signal(it->second));
+						log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", cell_type.c_str(), log_signal((*it).second));
 						YS_FALLTHROUGH
 					case FD_OUT:
 						sourceExpr = firstName;
 						sinkExpr = secondExpr;
 						sinkSig = &secondSig;
 						break;
 					case FD_NODIRECTION:
-						log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", cell_type.c_str(), log_signal(it->second));
+						log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", cell_type.c_str(), log_signal((*it).second));
 						YS_FALLTHROUGH
 					case FD_IN:
 						sourceExpr = secondExpr;
 						sinkExpr = firstName;
 						break;
 					default:
-						log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type.c_str(), log_signal(it->second), dir);
+						log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type.c_str(), log_signal((*it).second), dir);
 						break;
 				}
 				// Check for subfield assignment.
@@ -849,7 +849,7 @@ struct FirrtlWorker
 				}
 
 				auto it = cell->parameters.find(ID::B_SIGNED);
-				if (it == cell->parameters.end() || !it->second.as_bool()) {
+				if (it == cell->parameters.end() || !(*it).second.as_bool()) {
 					b_expr = "asUInt(" + b_expr + ")";
 				}
 
@@ -881,7 +881,7 @@ struct FirrtlWorker
 			if (cell->type.in(ID($mux), ID($_MUX_)))
 			{
 				auto it = cell->parameters.find(ID::WIDTH);
-				int width = it == cell->parameters.end()? 1 : it->second.as_int();
+				int width = it == cell->parameters.end()? 1 : (*it).second.as_int();
 				string a_expr = make_expr(cell->getPort(ID::A));
 				string b_expr = make_expr(cell->getPort(ID::B));
 				string s_expr = make_expr(cell->getPort(ID::S));

backends/intersynth/intersynth.cc

@@ -175,7 +175,7 @@ struct IntersynthBackend : public Backend {
 						node_code += stringf(" %s %s", log_id(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str());
 					}
 				}
-				for (auto &param : cell->parameters) {
+				for (auto param : cell->parameters) {
 					celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), log_id(param.first));
 					if (param.second.bits.size() != 32) {
 						node_code += stringf(" %s '", log_id(param.first));

backends/jny/jny.cc

@@ -342,11 +342,12 @@ struct JnyWriter
         }
     }
 
-    void write_prams(dict<RTLIL::IdString, RTLIL::Const>& params, uint16_t indent_level = 0) {
+    template <typename SmellsLikeDict>
+    void write_prams(SmellsLikeDict& params, uint16_t indent_level = 0) {
         const auto _indent = gen_indent(indent_level);
 
         bool first_param{true};
-        for (auto& param : params) {
+        for (auto param : params) {
             if (!first_param)
                 f << stringf(",\n");
             const auto param_val = param.second;

backends/json/json.cc

@@ -128,11 +128,11 @@ struct JsonWriter
 			f << get_string(value.as_string());
 		}
 	}
-
-	void write_parameters(const dict<IdString, Const> &parameters, bool for_module=false)
+	template <typename SmellsLikeDict>
+	void write_parameters(const SmellsLikeDict &parameters, bool for_module=false)
 	{
 		bool first = true;
-		for (auto &param : parameters) {
+		for (auto param : parameters) {
 			f << stringf("%s\n", first ? "" : ",");
 			f << stringf("        %s%s: ", for_module ? "" : "    ", get_name(param.first).c_str());
 			write_parameter_value(param.second);

backends/rtlil/rtlil_backend.cc

@@ -106,7 +106,7 @@ void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo
 	if (sig.is_chunk()) {
 		dump_sigchunk(f, sig.as_chunk(), autoint);
 	} else {
-		f << stringf("{ ");
+		f << stringf("{"); //FIXME this is a hack
 		for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); ++it) {
 			dump_sigchunk(f, *it, false);
 			f << stringf(" ");
@@ -165,7 +165,7 @@ void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::
 		f << stringf("\n");
 	}
 	f << stringf("%s" "cell %s %s\n", indent.c_str(), cell->type.c_str(), cell->name.c_str());
-	for (auto &it : cell->parameters) {
+	for (auto it : cell->parameters) {
 		f << stringf("%s  parameter%s%s %s ", indent.c_str(),
 				(it.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "",
 				(it.second.flags & RTLIL::CONST_FLAG_REAL) != 0 ? " real" : "",

backends/verilog/verilog_backend.cc

@@ -1895,9 +1895,9 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) {
 			if (it != cell->parameters.begin())
 				f << stringf(",");
-			f << stringf("\n%s  .%s(", indent.c_str(), id(it->first).c_str());
-			if (it->second.size() > 0)
-				dump_const(f, it->second);
+			f << stringf("\n%s  .%s(", indent.c_str(), id((*it).first).c_str());
+			if ((*it).second.size() > 0)
+				dump_const(f, (*it).second);
 			f << stringf(")");
 		}
 		f << stringf("\n%s" ")", indent.c_str());
@@ -1915,36 +1915,36 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		char str[16];
 		snprintf(str, 16, "$%d", i);
 		for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) {
-			if (it->first != str)
+			if ((*it).first != str)
 				continue;
 			if (!first_arg)
 				f << stringf(",");
 			first_arg = false;
 			f << stringf("\n%s  ", indent.c_str());
-			dump_sigspec(f, it->second);
-			numbered_ports.insert(it->first);
+			dump_sigspec(f, (*it).second);
+			numbered_ports.insert((*it).first);
 			goto found_numbered_port;
 		}
 		break;
 	found_numbered_port:;
 	}
 	for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) {
-		if (numbered_ports.count(it->first))
+		if (numbered_ports.count((*it).first))
 			continue;
 		if (!first_arg)
 			f << stringf(",");
 		first_arg = false;
-		f << stringf("\n%s  .%s(", indent.c_str(), id(it->first).c_str());
-		if (it->second.size() > 0)
-			dump_sigspec(f, it->second);
+		f << stringf("\n%s  .%s(", indent.c_str(), id((*it).first).c_str());
+		if ((*it).second.size() > 0)
+			dump_sigspec(f, (*it).second);
 		f << stringf(")");
 	}
 	f << stringf("\n%s" ");\n", indent.c_str());
 
 	if (defparam && cell->parameters.size() > 0) {
 		for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) {
-			f << stringf("%sdefparam %s.%s = ", indent.c_str(), cell_name.c_str(), id(it->first).c_str());
-			dump_const(f, it->second);
+			f << stringf("%sdefparam %s.%s = ", indent.c_str(), cell_name.c_str(), id((*it).first).c_str());
+			dump_const(f, (*it).second);
 			f << stringf(";\n");
 		}
 	}

flake.nix

@@ -14,22 +14,23 @@
         };
         # TODO: don't override src when ./abc is empty
         # which happens when the command used is `nix build` and not `nix build ?submodules=1`
-        abc-verifier = pkgs.abc-verifier.overrideAttrs(x: y: {src = ./abc;});
-        yosys = pkgs.clangStdenv.mkDerivation {
+        abc-verifier = pkgs.abc-verifier;
+        yosys = pkgs.llvmPackages.libcxxStdenv.mkDerivation {
           name = "yosys";
           src = ./. ;
-          buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git pkg-configUpstream ];
+          buildInputs = with pkgs; [ stdenv.cc.cc bison flex libffi tcl readline python3 zlib git pkg-configUpstream tracy ];
           checkInputs = with pkgs; [ gtest ];
           propagatedBuildInputs = [ abc-verifier ];
           preConfigure = "make config-clang";
           checkTarget = "test";
           installPhase = ''
-            make install PREFIX=$out ABCEXTERNAL=yosys-abc
+            make install PREFIX=$out ABCEXTERNAL=yosys-abc STRIP=\#
             ln -s ${abc-verifier}/bin/abc $out/bin/yosys-abc
           '';
 					buildPhase = ''
-            make -j$(nproc) ABCEXTERNAL=yosys-abc
+            make -j$(nproc) ABCEXTERNAL=yosys-abc PROFILER=tracy
           '';
+          dontStrip = true;
           meta = with pkgs.lib; {
             description = "Yosys Open SYnthesis Suite";
             homepage = "https://yosyshq.net/yosys/";
@@ -41,7 +42,7 @@
         packages.default = yosys;
         defaultPackage = yosys;
         devShell = pkgs.mkShell {
-          buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier ];
+          buildInputs = with pkgs; [ stdenv.cc.cc bison flex libffi tcl readline python3 zlib git gtest abc-verifier tracy ];
         };
       }
     );

frontends/aiger/aigerparse.cc

@@ -766,15 +766,17 @@ void AigerReader::post_process()
 {
 	unsigned ci_count = 0, co_count = 0;
 	for (auto cell : boxes) {
-		for (auto &bit : cell->connections_.at(ID(i))) {
+		auto sig_inp = cell->connections_.at(ID(i));
+		for (auto &bit : sig_inp) {
 			log_assert(bit == State::S0);
 			log_assert(co_count < outputs.size());
 			bit = outputs[co_count++];
 			log_assert(bit.wire && GetSize(bit.wire) == 1);
 			log_assert(bit.wire->port_output);
 			bit.wire->port_output = false;
 		}
-		for (auto &bit : cell->connections_.at(ID(o))) {
+		auto sig_outp = cell->connections_.at(ID(i));
+		for (auto &bit : sig_outp) {
 			log_assert(bit == State::S0);
 			log_assert((piNum + ci_count) < inputs.size());
 			bit = inputs[piNum + ci_count++];

frontends/ast/genrtlil.cc

@@ -2093,9 +2093,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			for (auto it = children.begin(); it != children.end(); it++) {
 				AstNode *child = *it;
 				if (child->type == AST_CELLTYPE) {
-					cell->type = child->str;
-					if (flag_icells && cell->type.begins_with("\\$"))
-						cell->type = cell->type.substr(1);
+					auto type = IdString(child->str);
+					if (flag_icells && type.begins_with("\\$"))
+						type = type.substr(1);
+					cell = cell->module->morphCell(type, cell);
 					continue;
 				}
 				if (child->type == AST_PARASET) {

frontends/blif/blifparse.cc

@@ -125,7 +125,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 	};
 
 	dict<RTLIL::IdString, RTLIL::Const> *obj_attributes = nullptr;
-	dict<RTLIL::IdString, RTLIL::Const> *obj_parameters = nullptr;
+	RTLIL::Cell::FakeParams *obj_parameters = nullptr;
 
 	dict<RTLIL::IdString, std::pair<int, bool>> wideports_cache;
 

frontends/json/jsonparse.cc

@@ -274,7 +274,8 @@ Const json_parse_attr_param_value(JsonNode *node)
 	return value;
 }
 
-void json_parse_attr_param(dict<IdString, Const> &results, JsonNode *node)
+template <typename SmellsLikeDict>
+void json_parse_attr_param(SmellsLikeDict &results, JsonNode *node)
 {
 	if (node->type != 'D')
 		log_error("JSON attributes or parameters node is not a dictionary.\n");

frontends/liberty/liberty.cc

@@ -269,21 +269,21 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
 	cell->setPort(ID::C, clk_sig);
 
 	if (clear_sig.size() == 0 && preset_sig.size() == 0) {
-		cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
+		cell = cell->module->morphCell(stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'), cell);
 	}
 
 	if (clear_sig.size() == 1 && preset_sig.size() == 0) {
-		cell->type = stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
+		cell = cell->module->morphCell(stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N'), cell);
 		cell->setPort(ID::R, clear_sig);
 	}
 
 	if (clear_sig.size() == 0 && preset_sig.size() == 1) {
-		cell->type = stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N');
+		cell = cell->module->morphCell(stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N'), cell);
 		cell->setPort(ID::R, preset_sig);
 	}
 
 	if (clear_sig.size() == 1 && preset_sig.size() == 1) {
-		cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
+		cell = cell->module->morphCell(stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N'), cell);
 		cell->setPort(ID::S, preset_sig);
 		cell->setPort(ID::R, clear_sig);
 	}

frontends/rpc/rpc_frontend.cc

@@ -207,7 +207,7 @@ struct RpcModule : RTLIL::Module {
 			for (auto module : derived_design->modules())
 				for (auto cell : module->cells())
 					if (name_mangling.count(cell->type.str()))
-						cell->type = name_mangling[cell->type.str()];
+						cell = cell->module->morphCell(name_mangling[cell->type.str()], cell);
 
 			for (auto module : derived_design->modules_) {
 				std::string mangled_name = name_mangling[module.first.str()];