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opt_reduce: keep at least one input to $reduce_or/and cells #4614

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Nov 20, 2024
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opt_reduce: keep at least one input to $reduce_or/and cells #4614

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023f029
opt_reduce: keep at least one input to $reduce_or/and cells
georgerennie Sep 25, 2024
0572f88
opt_reduce: add test for constant $reduce_and/or not being zero width
georgerennie Sep 25, 2024
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3 changes: 3 additions & 0 deletions passes/opt/opt_reduce.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -89,6 +89,9 @@ struct OptReduceWorker
RTLIL::SigSpec new_sig_a(new_sig_a_bits);
new_sig_a.sort_and_unify();

if (GetSize(new_sig_a) == 0)
new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1;

if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) {
log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
did_something = true;
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14 changes: 14 additions & 0 deletions tests/opt/opt_reduce_andor.ys
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@@ -0,0 +1,14 @@
# Check that opt_reduce doesn't produce zero width $reduce_or/$reduce_and,

read_verilog <<EOT
module reduce_const(output wire o, output wire a);
wire [3:0] zero = 4'b0000;
wire [3:0] ones = 4'b1111;
assign o = |zero;
assign a = &ones;
endmodule
EOT

equiv_opt -assert opt_reduce
design -load postopt
select -assert-none r:A_WIDTH=0
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