cxxrtl: fix vcd writer scope handling

[rroohhh]

The vcd writer incorrectly treated two scope vectors as the same, whenever they have the same length of entries and the last item matches. This is however not always true, for example consider a current_scope of ["top", "something0", "other_i"] and a scope of ["top", "something1", "other_i"] as one might obtain from the following verilog file:

module other2();
    wire w_inner;
endmodule

module other();
    other2 other_i();
endmodule


module top();
    other something0();
    other something1();
endmodule

The old code emitted a vcd of

$scope module top $end
$scope module something0 $end
$scope module other_i $end
$var wire 1 ! w_inner $end
$var wire 1 " w_inner $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
0!
0"

not changing the scope correctly for the two w_inner wires. This now correctly generates

$scope module top $end
$scope module something0 $end
$scope module other_i $end
$var wire 1 ! w_inner $end
$upscope $end
$upscope $end
$scope module something1 $end
$scope module other_i $end
$var wire 1 " w_inner $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
0!
0"