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dfflibmap: Adds flop name preserving pass to match write_verilog #4829

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QuantamHD
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What are the reasons/motivation for this change?
When using the dfflibmap pass it prevents write_verilog from adding proper flop names based on the Q output port. This makes it harder to read timing reports in OpenROAD. This code only works on internal flop types and does not work for cells mapped to standard cell modules.

See code in write_verilog:

if (!norename && cell->name[0] == '$' && RTLIL::builtin_ff_cell_types().count(cell->type) && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_)))
	{
		RTLIL::SigSpec sig = cell->getPort(ID::Q);
		if (GetSize(sig) != 1 || sig.is_fully_const())
			goto no_special_reg_name;

		RTLIL::Wire *wire = sig[0].wire;

		if (wire->name[0] != '\\')
			goto no_special_reg_name;

		std::string cell_name = wire->name.str();

		size_t pos = cell_name.find('[');
		if (pos != std::string::npos)
			cell_name = cell_name.substr(0, pos) + "_reg" + cell_name.substr(pos);
		else
			cell_name = cell_name + "_reg";

		if (wire->width != 1)
			cell_name += stringf("[%d]", wire->start_offset + sig[0].offset);

		if (active_module && active_module->count_id(cell_name) > 0)
				goto no_special_reg_name;

		return id(cell_name);
	}

Explain how this is achieved.

If the user passes -infer_flop_names to dfflibmap then it will attempt to rename flops based on the Q input port of the flop. This follows a similar renaming as in write_verilog, but that only works on $DFF and $dff based cell.

If applicable, please suggest to reviewers how they can test the change.

Pass -infer_flop_names to dfflibmap

If the user passes -infer_flop_names to dfflibmap then it will attempt
to rename flops based on the Q input port of the flop. This follows a
similar renaming as in write_verilog, but that only works on $DFF and
$dff based cell.

```c++
if (!norename && cell->name[0] == '$' && RTLIL::builtin_ff_cell_types().count(cell->type) && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_)))
	{
		RTLIL::SigSpec sig = cell->getPort(ID::Q);
		if (GetSize(sig) != 1 || sig.is_fully_const())
			goto no_special_reg_name;

		RTLIL::Wire *wire = sig[0].wire;

		if (wire->name[0] != '\\')
			goto no_special_reg_name;

		std::string cell_name = wire->name.str();

		size_t pos = cell_name.find('[');
		if (pos != std::string::npos)
			cell_name = cell_name.substr(0, pos) + "_reg" + cell_name.substr(pos);
		else
			cell_name = cell_name + "_reg";

		if (wire->width != 1)
			cell_name += stringf("[%d]", wire->start_offset + sig[0].offset);

		if (active_module && active_module->count_id(cell_name) > 0)
				goto no_special_reg_name;

		return id(cell_name);
	}
```
@QuantamHD
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@povik Mind taking a look when you're back from break?

@povik
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povik commented Jan 2, 2025

How does this compare to running the rename -wire command post dfflibmap?

    rename -wire [selection] [-suffix <suffix>]

Assign auto-generated names based on the wires they drive to all selected
cells with private names. Ignores cells driving privatly named wires.
By default, the cell is named after the wire with the cell type as suffix.
The -suffix option can be used to set the suffix to the given string instead.

@QuantamHD
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hmm, let me check to see. I didn't know about that command.

@povik
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povik commented Jan 2, 2025

Fwiw ORFS does use it in their script

@QuantamHD
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Yeah that definitely works. It's a little bit different than what comes out of write_verilog, but IMO close enough. Thanks @povik

@QuantamHD QuantamHD closed this Jan 2, 2025
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2 participants