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Add KR260 reference design example #150

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vmayoral
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@vmayoral vmayoral commented Mar 9, 2023

Connected to #146.

Signed-off-by: Víctor Mayoral Vilches <[email protected]>
@vmayoral vmayoral mentioned this pull request Mar 9, 2023
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@alexforencich
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Please make sure this is clear of any output files (there are some under tb that should be removed). Also, if there are no button/switch inputs, there is no need for debounce_switch. Please also clean up all of the commented out code - if it's not relevant to the KR260, it should be deleted completely.

Also, I don't think the KR260 requires a Vivado license, so that language should probably be removed from the readme.

@alexforencich
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Also, if this is for the SFP+ module and the board also has 1G interfaces, please rename KR260/fpga to KR260/fpga_10g so that later on KR260/fpga_1g can be added.

Signed-off-by: Víctor Mayoral Vilches <[email protected]>
Signed-off-by: Víctor Mayoral Vilches <[email protected]>
@vmayoral
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Addressed comments above @alexforencich, let me know if you're missing anything.

Modified while testing things locally

Signed-off-by: Víctor Mayoral Vilches <[email protected]>
@vmayoral
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Nit added at 2e69f50, left-over from dev changes. Consistent now with the rest of the repo.

Signed-off-by: Víctor Mayoral Vilches <[email protected]>
@vmayoral
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Renamed also as requested above @alexforencich.

@russell-t
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@vmayoral I tried compiling the 10g example using Vivado 2023.1. I get errors that module 'zynq_ps' is not found resulting in synthesis failing. Opening fpga.xpr in Vivado, I see that zynq_ps_inst, gtkwizard_ultrascale_v1_7_16.eth_xcvr_gt_full_gtwizard_gthe3, gtkwizard_ultrascale_v1_7_16.eth_xcvr_gt_full_gtwizard_gtye3,
gtkwizard_ultrascale_v1_7_16.eth_xcvr_gt_full_gtwizard_gtye4, and eth_xcvr_gt_channel all have a question mark next to their names.

@vmayoral
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Hey @russell-t,

It's been a while since I looked at this last time. Note that this reference design was built with Vitis/Vivado 2022.1 (see #146). I'd encourage you to try things out with that version instead.

Cheers,

@vmayoral
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Closing this ticket to avoid idle PRs around. Feel free to re-open/rebase/merge if of interest at some point in the future.

I'll leave the submitted version at the following branch alive: https://github.com/vmayoral/verilog-ethernet/tree/kr260-pr

@vmayoral vmayoral closed this Aug 25, 2023
@alexforencich
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@russell-t you need to source all of the TCL files in the ip directory.

@vmayoral we should definitely get KR260 support merged in some form. Do you want to work on this PR a bit more, or should I just put together a set of reference designs myself for the different interfaces on the KR260?

@vmayoral
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@vmayoral we should definitely get KR260 support merged in some form. Do you want to work on this PR a bit more, or should I just put together a set of reference designs myself for the different interfaces on the KR260?

@alexforencich happy to rework it if needed, sure. Any particular fixes that you miss in here? Branch per se is operational as per my last testing and addressed your previous comments. Let me know if you're missing anything else.

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3 participants