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Add KR260 reference design example#150

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vmayoral wants to merge 6 commits intoalexforencich:masteralexforencich/verilog-ethernet:masterfrom vmayoral:kr260-prvmayoral/verilog-ethernet:kr260-prCopy head branch name to clipboard

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Commits on Mar 9, 2023

• Add KR260 reference design example

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Commits on Mar 10, 2023

• Remove TB build results

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• Remove debounce_switch and clean up code

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• Update README, remove license needs, part of WEBPACK

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• Re-instantiate the same IP used in other TBs

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Commits on Mar 11, 2023

• Rename reference design to fpga_10g

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