Example for Digilent Genesys2 board (XC7K325T)

README.md

@@ -40,6 +40,7 @@ following boards:
 *  BittWare 520N-MX (Intel Stratix 10 MX 1SM21CHU2F53E2VG)
 *  Digilent Arty A7 (Xilinx Artix 7 XC7A35T)
 *  Digilent Atlys (Xilinx Spartan 6 XC6SLX45)
+*  Digilent Genesys2 (Xilinx Kintex 7 XC7K325T)
 *  Intel Cyclone 10 LP (Intel Cyclone 10 10CL025YU256I7G)
 *  Terasic DE2-115 (Intel Cyclone IV E EP4CE115F29C7)
 *  Terasic DE5-Net (Intel Stratix V 5SGXEA7N2F45C2)

example/Genesys2/fpga_rgmii/Makefile

@@ -0,0 +1,25 @@
+# Targets
+TARGETS:=
+
+# Subdirectories
+SUBDIRS = fpga
+SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
+
+# Rules
+.PHONY: all
+all: $(SUBDIRS) $(TARGETS)
+
+.PHONY: $(SUBDIRS)
+$(SUBDIRS):
+	cd $@ && $(MAKE)
+
+.PHONY: $(SUBDIRS_CLEAN)
+$(SUBDIRS_CLEAN):
+	cd $(@:.clean=) && $(MAKE) clean
+
+.PHONY: clean
+clean: $(SUBDIRS_CLEAN)
+	-rm -rf $(TARGETS)
+
+program:
+	#djtgcfg prog -d Genesys2 --index 0 --file fpga/fpga.bit

example/Genesys2/fpga_rgmii/README.md

@@ -0,0 +1,30 @@
+# Verilog Ethernet Genesys2 Example Design
+
+## Introduction
+
+This example design targets the Digilent Genesys2 FPGA board.
+
+The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
+will echo back any packets received.  The design will also respond correctly
+to ARP requests.  
+
+*  FPGA: XC7K325T-2FFG900C
+*  PHY: Realtek RTL8211E-VL
+
+## How to build
+
+Run make to build.  Ensure that the Xilinx Vivado toolchain components are
+in PATH.  
+
+## How to test
+
+Run make program to program the Genesys2 board with Vivado.  Then run
+
+    netcat -u 192.168.1.128 1234
+
+to open a UDP connection to port 1234.  Any text entered into netcat will be
+echoed back after pressing enter.
+
+It is also possible to use hping to test the design by running
+
+    hping 192.168.1.128 -2 -p 1234 -d 1024

example/Genesys2/fpga_rgmii/common/vivado.mk

@@ -0,0 +1,123 @@
+###################################################################
+# 
+# Xilinx Vivado FPGA Makefile
+# 
+# Copyright (c) 2016 Alex Forencich
+# 
+###################################################################
+# 
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - space-separated list of source files
+# INC_FILES - space-separated list of include files
+# XDC_FILES - space-separated list of timing constraint files
+# XCI_FILES - space-separated list of IP XCI files
+# 
+# Example:
+# 
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+# 
+###################################################################
+
+# phony targets
+.PHONY: clean fpga
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include ../$(CONFIG)
+
+SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES))
+INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES))
+XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES))
+IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES))
+
+ifdef XDC_FILES
+  XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES))
+else
+  XDC_FILES_REL = $(FPGA_TOP).xdc
+endif
+
+###################################################################
+# Main Targets
+#
+# all: build everything
+# clean: remove output files and project files
+###################################################################
+
+all: fpga
+
+fpga: $(FPGA_TOP).bit
+
+vivado: $(FPGA_TOP).xpr
+	vivado $(FPGA_TOP).xpr
+
+tmpclean:
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean: tmpclean
+	-rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+
+distclean: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+%.xpr: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $*" > create_project.tcl
+	echo "add_files -fileset sources_1 defines.v" >> create_project.tcl
+	for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done
+	for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done
+	for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done
+	for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done
+	echo "exit" >> create_project.tcl
+	vivado -nojournal -nolog -mode batch -source create_project.tcl
+
+# synthesis run
+%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
+	echo "open_project $*.xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	echo "exit" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
+	echo "open_project $*.xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "exit" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# bit file
+%.bit: %.runs/impl_1/%_routed.dcp
+	echo "open_project $*.xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force $*.bit" >> generate_bit.tcl
+	echo "exit" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	mkdir -p rev
+	EXT=bit; COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp $@ rev/$*_rev$$COUNT.$$EXT; \
+	echo "Output: rev/$*_rev$$COUNT.$$EXT";

example/Genesys2/fpga_rgmii/eth.xdc

@@ -0,0 +1,5 @@
+# Ethernet constraints
+
+# IDELAY on RGMII from PHY chip
+set_property IDELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_*}]
+

example/Genesys2/fpga_rgmii/fpga.xdc

@@ -0,0 +1,90 @@
+# XDC constraints for the Digilent Genesys 2 Rev. H board
+# part: xc7k325tffg900c
+# Adapted for Digilent Genesys2 board by Torsten Reuschel 2021
+
+# General configuration
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
+
+# System clocks
+# 200 MHz
+set_property -dict {PACKAGE_PIN AD11  IOSTANDARD LVDS} [get_ports { clk_200mhz_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
+set_property -dict {PACKAGE_PIN AD12  IOSTANDARD LVDS} [get_ports { clk_200mhz_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
+create_clock -period 5.000 -name clk_200mhz [get_ports clk_200mhz_p]
+
+# LEDs
+set_property -dict {PACKAGE_PIN T28   IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports { led[0] }]; #IO_L11N_T1_SRCC_14 Sch=led[0]
+set_property -dict {PACKAGE_PIN V19   IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports { led[1] }]; #IO_L19P_T3_A10_D26_14 Sch=led[1]
+set_property -dict {PACKAGE_PIN U30   IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports { led[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[2]
+set_property -dict {PACKAGE_PIN U29   IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports { led[3] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=led[3]
+set_property -dict {PACKAGE_PIN V20   IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports { led[4] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=led[4]
+set_property -dict {PACKAGE_PIN V26   IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports { led[5] }]; #IO_L16P_T2_CSI_B_14 Sch=led[5]
+set_property -dict {PACKAGE_PIN W24   IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports { led[6] }]; #IO_L20N_T3_A07_D23_14 Sch=led[6]
+set_property -dict {PACKAGE_PIN W23   IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports { led[7] }]; #IO_L20P_T3_A08_D24_14 Sch=led[7]
+
+set_false_path -to [get_ports { led[*] }]
+set_output_delay 0 [get_ports { led[*] }]
+
+# Reset button
+set_property -dict {PACKAGE_PIN R19   IOSTANDARD LVCMOS33} [get_ports { reset_n }]; #IO_0_14 Sch=cpu_resetn
+
+set_false_path -from [get_ports { reset_n }]
+set_input_delay 0 [get_ports { reset_n }]
+
+# Push buttons
+set_property -dict {PACKAGE_PIN E18   IOSTANDARD LVCMOS12} [get_ports { btnc }]; #IO_25_17 Sch=btnc
+set_property -dict {PACKAGE_PIN M19   IOSTANDARD LVCMOS12} [get_ports { btnd }]; #IO_0_15 Sch=btnd
+set_property -dict {PACKAGE_PIN M20   IOSTANDARD LVCMOS12} [get_ports { btnl }]; #IO_L6P_T0_15 Sch=btnl
+set_property -dict {PACKAGE_PIN C19   IOSTANDARD LVCMOS12} [get_ports { btnr }]; #IO_L24P_T3_17 Sch=btnr
+set_property -dict {PACKAGE_PIN B19   IOSTANDARD LVCMOS12} [get_ports { btnu }]; #IO_L24N_T3_17 Sch=btnu
+
+set_false_path -from [get_ports { btnu btnl btnd btnr btnc }]
+set_input_delay 0 [get_ports { btnu btnl btnd btnr btnc }]
+
+# Toggle switches
+set_property -dict {PACKAGE_PIN G19   IOSTANDARD LVCMOS12} [get_ports { sw[0] }]; #IO_0_17 Sch=sw[0]
+set_property -dict {PACKAGE_PIN G25   IOSTANDARD LVCMOS12} [get_ports { sw[1] }]; #IO_25_16 Sch=sw[1]
+set_property -dict {PACKAGE_PIN H24   IOSTANDARD LVCMOS12} [get_ports { sw[2] }]; #IO_L19P_T3_16 Sch=sw[2]
+set_property -dict {PACKAGE_PIN K19   IOSTANDARD LVCMOS12} [get_ports { sw[3] }]; #IO_L6P_T0_17 Sch=sw[3]
+
+set_false_path -from [get_ports { sw[*] }]
+set_input_delay 0 [get_ports { sw[*] }]
+
+# UART
+set_property -dict {PACKAGE_PIN Y20   IOSTANDARD LVCMOS33                   } [get_ports { uart_rxd }]; #IO_0_12 Sch=uart_tx_in
+set_property -dict {PACKAGE_PIN Y23   IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports { uart_txd }]; #IO_L1P_T0_12 Sch=uart_rx_out
+#set_property -dict { PACKAGE_PIN Y20   IOSTANDARD LVCMOS33 } [get_ports { uart_txd }]; #IO_0_12 Sch=uart_tx_in
+#set_property -dict { PACKAGE_PIN Y23   IOSTANDARD LVCMOS33 } [get_ports { uart_rxd }]; #IO_L1P_T0_12 Sch=uart_rx_out
+
+set_false_path -to [get_ports {uart_txd}]
+set_output_delay 0 [get_ports {uart_txd}]
+set_false_path -from [get_ports {uart_rxd}]
+set_input_delay 0 [get_ports {uart_rxd}]
+
+# Gigabit Ethernet GMII PHY
+set_property -dict {PACKAGE_PIN AG10  IOSTANDARD LVCMOS15                   } [get_ports { phy_rx_clk }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk
+set_property -dict {PACKAGE_PIN AJ14  IOSTANDARD LVCMOS15                   } [get_ports { phy_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0]
+set_property -dict {PACKAGE_PIN AH14  IOSTANDARD LVCMOS15                   } [get_ports { phy_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1]
+set_property -dict {PACKAGE_PIN AK13  IOSTANDARD LVCMOS15                   } [get_ports { phy_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2]
+set_property -dict {PACKAGE_PIN AJ13  IOSTANDARD LVCMOS15                   } [get_ports { phy_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3]
+set_property -dict {PACKAGE_PIN AH11  IOSTANDARD LVCMOS15                   } [get_ports { phy_rx_ctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl
+set_property -dict {PACKAGE_PIN AE10  IOSTANDARD LVCMOS15 SLEW FAST DRIVE 16} [get_ports { phy_tx_clk }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
+set_property -dict {PACKAGE_PIN AJ12  IOSTANDARD LVCMOS15 SLEW FAST DRIVE 16} [get_ports { phy_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0]
+set_property -dict {PACKAGE_PIN AK11  IOSTANDARD LVCMOS15 SLEW FAST DRIVE 16} [get_ports { phy_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1]
+set_property -dict {PACKAGE_PIN AJ11  IOSTANDARD LVCMOS15 SLEW FAST DRIVE 16} [get_ports { phy_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2]
+set_property -dict {PACKAGE_PIN AK10  IOSTANDARD LVCMOS15 SLEW FAST DRIVE 16} [get_ports { phy_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3]
+set_property -dict {PACKAGE_PIN AK14  IOSTANDARD LVCMOS15 SLEW FAST DRIVE 16} [get_ports { phy_tx_ctl }]; #IO_L20P_T3_33 Sch=eth_tx_en
+set_property -dict {PACKAGE_PIN AH24  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports { phy_reset_n }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n
+set_property -dict {PACKAGE_PIN AK16  IOSTANDARD LVCMOS18                   } [get_ports { phy_int_n }]; #IO_L1P_T0_32 Sch=eth_intb
+#set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS18} [get_ports phy_pme_n]
+#set_property -dict {PACKAGE_PIN AG12  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports phy_mdio]
+#set_property -dict {PACKAGE_PIN AF12  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports phy_mdc]
+
+create_clock -period 8.000 -name phy_rx_clk [get_ports phy_rx_clk]
+
+set_false_path -to [get_ports { phy_reset_n }]
+set_output_delay 0 [get_ports { phy_reset_n }]
+set_false_path -from [get_ports { phy_int_n }]
+set_input_delay 0 [get_ports { phy_int_n }]
+

example/Genesys2/fpga_rgmii/fpga/Makefile

@@ -0,0 +1,67 @@
+
+# FPGA settings
+FPGA_PART = xc7k325tffg900-2
+FPGA_TOP = fpga
+FPGA_ARCH = kintex7
+
+# Files for synthesis
+SYN_FILES = rtl/fpga.v
+SYN_FILES += rtl/fpga_core.v
+SYN_FILES += rtl/debounce_switch.v
+SYN_FILES += rtl/sync_signal.v
+SYN_FILES += lib/eth/rtl/iddr.v
+SYN_FILES += lib/eth/rtl/oddr.v
+SYN_FILES += lib/eth/rtl/ssio_ddr_in.v
+SYN_FILES += lib/eth/rtl/rgmii_phy_if.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g_rgmii_fifo.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g_rgmii.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g.v
+SYN_FILES += lib/eth/rtl/axis_gmii_rx.v
+SYN_FILES += lib/eth/rtl/axis_gmii_tx.v
+SYN_FILES += lib/eth/rtl/lfsr.v
+SYN_FILES += lib/eth/rtl/eth_axis_rx.v
+SYN_FILES += lib/eth/rtl/eth_axis_tx.v
+SYN_FILES += lib/eth/rtl/udp_complete.v
+SYN_FILES += lib/eth/rtl/udp_checksum_gen.v
+SYN_FILES += lib/eth/rtl/udp.v
+SYN_FILES += lib/eth/rtl/udp_ip_rx.v
+SYN_FILES += lib/eth/rtl/udp_ip_tx.v
+SYN_FILES += lib/eth/rtl/ip_complete.v
+SYN_FILES += lib/eth/rtl/ip.v
+SYN_FILES += lib/eth/rtl/ip_eth_rx.v
+SYN_FILES += lib/eth/rtl/ip_eth_tx.v
+SYN_FILES += lib/eth/rtl/ip_arb_mux.v
+SYN_FILES += lib/eth/rtl/arp.v
+SYN_FILES += lib/eth/rtl/arp_cache.v
+SYN_FILES += lib/eth/rtl/arp_eth_rx.v
+SYN_FILES += lib/eth/rtl/arp_eth_tx.v
+SYN_FILES += lib/eth/rtl/eth_arb_mux.v
+SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
+SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
+SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
+
+# XDC files
+XDC_FILES = fpga.xdc
+XDC_FILES += eth.xdc
+XDC_FILES += lib/eth/syn/vivado/rgmii_phy_if.tcl
+XDC_FILES += lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl
+XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
+XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
+XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+

example/Genesys2/fpga_rgmii/fpga/generate_bit_iodelay.tcl

@@ -0,0 +1,6 @@
+open_project fpga.xpr
+open_run impl_1
+set_property IDELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_*}]
+set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst]
+write_bitstream -force fpga.bit
+exit

example/Genesys2/fpga_rgmii/lib/eth

@@ -0,0 +1 @@
+../../../../