Added VMK180 example design

[corco]

This adds the example design for the VMK180. Technically, it also adds support for the VCK190, which is identical (just changing the part number and keeping everything as is should work). However, I cannot test on VCK190 so I didn't add it.

VMK180 uses the Versal's CPM4 module to provide a PCIe Gen4 x8. Although more recent than the Ultrascale+ devices currently in the repo, the Versal CPM's PCIe interface is compatible. There are new fields in _tuser, but they are unused and are here ignored.

I based the files on the VCU118 example. VCU118 had PCIe Gen3 x16, which has the same bandwidth/interface as the VMK180, thus minimal modification was required.

[alexforencich]

That's interesting, I was under the impression that the CPM block could only be used via the NoC, and there was a separate core that could be used from the fabric. But I don't have any versal hardware so I haven't had a chance to really dig in to the architecture.

Unfortunately there are a couple of issues here. First is that I cannot accept code that I cannot maintain. I do not have access to the VMK180/VCK190, or any Versal parts for that matter, so I cannot maintain any code that targets the Versal line unless I procure some Versal hardware. The second problem is that this repository is effectively deprecated and will be replaced by https://github.com/fpganinja/taxi. As a result, I will not be adding any new features or new FPGA families to this repo. However, I would be happy to add Versal support to the Taxi library once I have the PCIe code ported over to SV and have access to Versal hardware for testing.

[corco]

I understand, feel free to use the code for when you get your hand on a Versal device.

As far as Versal and PCIe goes, Versal has CPM modules and hard PCIe blocks. CPM has 2 PCIe hard controllers and 1 optional DMA engine that can connect to either PCIe controller. That DMA engine has dedicated connection to the NoC. To use both PCIe controllers in the CPM, you must minimally roll your own logic on 1 of them.

As far as I understand, the advantage of the CPM PCIe controller compared to the logic ones is that it is part of the PS. As such, it doesn't require any bitstream to configure and is thus ready quickly after powerup. On older architecture, you had more work to ensure PCIe core & PCIe Reset were configured early enough to respect PCIe boot time.