Dcache rr

chip_top/AnyCore_Piton.sv

@@ -103,18 +103,20 @@ module AnyCore_Piton(
 
 wire [`ICACHE_BLOCK_ADDR_BITS-1:0] ic2memReqAddr;    // memory read address
 wire                               ic2memReqValid;   // memory read enable
+wire [`ICACHE_NUM_WAYS_LOG-1:0]                        ic2memReqWay;     // memory way 
 wire [`ICACHE_TAG_BITS-1:0]        mem2icTag;        // tag of the incoming data
 wire [`ICACHE_INDEX_BITS-1:0]      mem2icIndex;      // index of the incoming data
 wire [`ICACHE_BITS_IN_LINE-1:0]    mem2icData;       // requested data
 wire                               mem2icRespValid;  // requested data is ready
 
 wire                               mem2icInv;        // icache invalidation
 wire  [`ICACHE_INDEX_BITS-1:0]     mem2icInvInd;     // icache invalidation index
-wire  [0:0]                        mem2icInvWay;     // icache invalidation way (unused)
+wire  [`ICACHE_NUM_WAYS_LOG-1:0]                        mem2icInvWay;     // icache invalidation way (unused)
 
 // cache-to-memory interface for Loads
 wire [`DCACHE_BLOCK_ADDR_BITS-1:0] dc2memLdAddr;  // memory read address
 wire                               dc2memLdValid; // memory read enable
+wire [1:0]                         dc2memReqWay;  // memory way
 
 // memory-to-cache interface for Loads
 wire [`DCACHE_TAG_BITS-1:0]     mem2dcLdTag;       // tag of the incoming datadetermine
@@ -130,7 +132,7 @@ wire                             dc2memStValid;
 
 wire                               mem2dcInv;     // dcache invalidation
 wire  [`DCACHE_INDEX_BITS-1:0]     mem2dcInvInd;  // dcache invalidation index
-wire  [0:0]                        mem2dcInvWay;  // dcache invalidation way (unused)
+wire  [1:0]                        mem2dcInvWay;  // dcache invalidation way (unused)
 
 wire                            mem2dcStComplete;
 wire                            mem2dcStStall;
@@ -448,6 +450,7 @@ Core_OOO coreTop(
   `ifdef INST_CACHE
     .ic2memReqAddr_o                     (ic2memReqAddr  ),      // memory read address
     .ic2memReqValid_o                    (ic2memReqValid ),     // memory read enable
+    .ic2memReqWay_o                      (ic2memReqWay),
     .mem2icTag_i                         (mem2icTag      ),          // tag of the incoming data
     .mem2icIndex_i                       (mem2icIndex    ),        // index of the incoming data
     .mem2icData_i                        (mem2icData     ),         // requested data
@@ -472,6 +475,7 @@ Core_OOO coreTop(
 
     .dc2memLdAddr_o                      (dc2memLdAddr     ), // memory read address
     .dc2memLdValid_o                     (dc2memLdValid    ), // memory read enable
+    .dc2memReqWay_o                      (dc2memReqWay     ),
 
     .mem2dcLdTag_i                       (mem2dcLdTag      ), // tag of the incoming datadetermine
     .mem2dcLdIndex_i                     (mem2dcLdIndex    ), // index of the incoming data
@@ -586,6 +590,7 @@ Core_OOO coreTop(
 //`endif
 
 
+    //DO WE EVEN NEED TO ADD STUFF HERE?
     // not supported at the moment
     assign transducer_l15_amo_op = `L15_AMO_OP_NONE;
     anycore_tri_transducer tri_transducer(
@@ -597,6 +602,9 @@ Core_OOO coreTop(
 
         .ic2mem_reqaddr_i                  (ic2memReqAddr),
         .ic2mem_reqvalid_i                 (ic2memReqValid),
+        .ic2memReqWay_o                    (ic2memReqWay),
+        .dc2memReqWay_o                    (dc2memReqWay),
+
 
         .dc2mem_ldaddr_i                   (dc2memLdAddr),
         .dc2mem_ldvalid_i                  (dc2memLdValid),

chip_top/anycore_tri_transducer.v

@@ -10,6 +10,8 @@ module anycore_tri_transducer(
 
     input [`ICACHE_BLOCK_ADDR_BITS-1:0] ic2mem_reqaddr_i,
     input                               ic2mem_reqvalid_i,
+    output [`ICACHE_NUM_WAYS_LOG-1:0]                        ic2memReqWay_o,
+    output [1:0]                                             dc2memReqWay_o,
 
     input [`DCACHE_BLOCK_ADDR_BITS-1:0] dc2mem_ldaddr_i,
 
@@ -58,6 +60,7 @@ module anycore_tri_transducer(
     input wire [1:0]    l15_transducer_cross_invalidate_way_i,
     input wire          l15_transducer_inval_dcache_inval_i,
     input wire          l15_transducer_inval_icache_inval_i,
+    //said something about this wire
     input wire [1:0]    l15_transducer_inval_way_i,
     input wire          l15_transducer_blockinitstore_i,
 
@@ -76,11 +79,11 @@ module anycore_tri_transducer(
 
     output                              mem2dc_invvalid_o,
     output [`DCACHE_INDEX_BITS-1:0]     mem2dc_invindex_o,
-    output [0:0]                        mem2dc_invway_o,
+    output [1:0]                        mem2dc_invway_o,
 
     output                              mem2ic_invvalid_o,
     output [`ICACHE_INDEX_BITS-1:0]     mem2ic_invindex_o,
-    output [0:0]                        mem2ic_invway_o,
+    output [`ICACHE_NUM_WAYS_LOG-1:0]                        mem2ic_invway_o,
 
     input                               dc2mem_stvalid_i,
     output reg                          mem2dc_stcomplete_o,
@@ -98,14 +101,17 @@ reg header_ack_seen_reg;
 // Get full address that's 64 bits long since it's otherwise to icache
 // block alignment
 wire [63:0] anycore_imiss_full_addr = ic2mem_reqaddr_i << (64-`ICACHE_BLOCK_ADDR_BITS);
-wire [1:0] anycore_imiss_way = ic2mem_reqaddr_i[`ICACHE_INDEX_BITS-1:`ICACHE_INDEX_BITS-2-1];
+//CHANGES
+//wire [1:0] anycore_imiss_way = ic2mem_reqaddr_i[`ICACHE_INDEX_BITS-1:`ICACHE_INDEX_BITS-2-1];
+wire [`ICACHE_NUM_WAYS_LOG-1:0] anycore_imiss_way = ic2memReqWay_o;
+
 // Sign extend to 64 bits
 //wire [63:0] anycore_store_full_addr = {{((64-`DCACHE_ST_ADDR_BITS)-3){dc2mem_staddr_i[`DCACHE_ST_ADDR_BITS-1]}}, (dc2mem_staddr_i << 3)};
 wire [63:0] anycore_store_full_addr = {{((64-`DCACHE_ST_ADDR_BITS)-3){dc2mem_staddr_i[`DCACHE_ST_ADDR_BITS-1]}}, (dc2mem_staddr_i)};
-wire [1:0] anycore_store_way = dc2mem_staddr_i[`DCACHE_INDEX_BITS-1:`DCACHE_INDEX_BITS-2-1];
+wire [1:0] anycore_store_way = dc2memReqWay_o; // dc2mem_staddr_i[`DCACHE_INDEX_BITS-1:`DCACHE_INDEX_BITS-2-1];
 // Sign extend to 64 bits
 wire [63:0] anycore_load_full_addr = {{((64-`DCACHE_BLOCK_ADDR_BITS)-4){dc2mem_ldaddr_i[`DCACHE_BLOCK_ADDR_BITS-1]}}, (dc2mem_ldaddr_i << 4)};
-wire [1:0] anycore_load_way = dc2mem_ldaddr_i[`DCACHE_INDEX_BITS-1:`DCACHE_INDEX_BITS-2-1];
+wire [1:0] anycore_load_way = dc2memReqWay_o; // dc2mem_ldaddr_i[`DCACHE_INDEX_BITS-1:`DCACHE_INDEX_BITS-2-1];
 
 wire [63:0] anycore_dc2mem_stdata_flipped = {dc2mem_stdata_i[7:0], dc2mem_stdata_i[15:8], dc2mem_stdata_i[23:16], dc2mem_stdata_i[31:24], dc2mem_stdata_i[39:32], dc2mem_stdata_i[47:40], dc2mem_stdata_i[55:48], dc2mem_stdata_i[63:56]};
 //wire [63:0] anycore_dc2mem_stdata_flipped = dc2mem_stdata_i;
@@ -411,9 +417,13 @@ end
 
 assign mem2dc_invvalid_o = signal_dcache_inval & ~dinvalrst_reg;
 assign mem2ic_invvalid_o = signal_icache_inval & ~iinvalrst_reg;
-assign mem2dc_invway_o = l15_transducer_inval_way_i;
+//CHANGES
+assign mem2dc_invway_o = dc2memReqWay_o;
+//assign mem2dc_invway_o = ic2memReqWay_o;
 assign mem2dc_invindex_o = l15_transducer_inval_address_15_4_i[`DCACHE_INDEX_BITS+4-1:4];
-assign mem2ic_invway_o = l15_transducer_inval_way_i;
+//assign mem2ic_invway_o = 1; //l15_transducer_inval_way_i;
+assign mem2ic_invway_o = ic2memReqWay_o;
+//assign mem2ic_invway_o = mem2icInvWay_i;
 assign mem2ic_invindex_o = l15_transducer_inval_address_15_4_i[`DCACHE_INDEX_BITS+4-1:4];
 
 always @ * begin

configs/CommonConfig.h

@@ -255,14 +255,16 @@
   `define ICACHE_BITS_IN_LINE (`ICACHE_INSTS_IN_LINE*`SIZE_INSTRUCTION)  //In bits
   `define ICACHE_BYTES_IN_LINE (`ICACHE_BITS_IN_LINE/8) 
   `define ICACHE_BYTES_IN_LINE_LOG (`ICACHE_INSTS_IN_LINE_LOG + `ICACHE_INST_BYTE_OFFSET_LOG) //log2(ICACHE_BYTES_IN_LINE)
-  `define ICACHE_NUM_LINES 64 //128
-  `define ICACHE_NUM_LINES_LOG 6 //7
+  `define ICACHE_NUM_LINES 16 //128
+  `define ICACHE_NUM_LINES_LOG 4 //7
   `define ICACHE_OFFSET_BITS  `ICACHE_INSTS_IN_LINE_LOG
   `define ICACHE_INDEX_BITS   `ICACHE_NUM_LINES_LOG
   `define ICACHE_TAG_BITS     (`SIZE_PC - `ICACHE_INDEX_BITS - `ICACHE_OFFSET_BITS - `ICACHE_INST_BYTE_OFFSET_LOG)
   `define ICACHE_BLOCK_ADDR_BITS  (`SIZE_PC - `ICACHE_OFFSET_BITS - `ICACHE_INST_BYTE_OFFSET_LOG) // Cache block address 
   `define ICACHE_PC_PKT_BITS    8
   `define ICACHE_INST_PKT_BITS  8
+  `define ICACHE_NUM_WAYS 4
+  `define ICACHE_NUM_WAYS_LOG 2
 `endif
 
 `ifdef DATA_CACHE

core_top/Core_OOO.sv

@@ -54,14 +54,16 @@ module Core_OOO(
 `ifdef INST_CACHE
   output [`ICACHE_BLOCK_ADDR_BITS-1:0]ic2memReqAddr_o,      // memory read address
   output                              ic2memReqValid_o,     // memory read enable
+  output [`ICACHE_NUM_WAYS_LOG-1:0]  					  ic2memReqWay_o,
+
   input  [`ICACHE_TAG_BITS-1:0]       mem2icTag_i,          // tag of the incoming data
   input  [`ICACHE_INDEX_BITS-1:0]     mem2icIndex_i,        // index of the incoming data
   input  [`ICACHE_BITS_IN_LINE-1:0]   mem2icData_i,         // requested data
   input                               mem2icRespValid_i,    // requested data is ready
 
   input                               mem2icInv_i,          // icache invalidation
   input  [`ICACHE_INDEX_BITS-1:0]     mem2icInvInd_i,       // icache invalidation index
-  input  [0:0]                        mem2icInvWay_i,       // icache invalidation way (unused)
+  input  [`ICACHE_NUM_WAYS_LOG-1:0]                        mem2icInvWay_i,       // icache invalidation way (unused)
 
   //input                               instCacheBypass_i,
   input                               icScratchModeEn_i,    // Should ideally be disabled by default
@@ -78,6 +80,7 @@ module Core_OOO(
   // cache-to-memory interface for Loads
   output [`DCACHE_BLOCK_ADDR_BITS-1:0]dc2memLdAddr_o,  // memory read address
   output reg                          dc2memLdValid_o, // memory read enable
+  output [1:0]  dc2memReqWay_o,
 
   // memory-to-cache interface for Loads
   input  [`DCACHE_TAG_BITS-1:0]       mem2dcLdTag_i,       // tag of the incoming datadetermine
@@ -93,7 +96,7 @@ module Core_OOO(
 
   input                               mem2dcInv_i,     // dcache invalidation
   input  [`DCACHE_INDEX_BITS-1:0]     mem2dcInvInd_i,  // dcache invalidation index
-  input  [0:0]                        mem2dcInvWay_i,  // dcache invalidation way (unused)
+  input  [1:0]                        mem2dcInvWay_i,  // dcache invalidation way (unused)
 
   // memory-to-cache interface for stores
   input                               mem2dcStComplete_i,
@@ -501,6 +504,7 @@ FetchStage1 fs1(
 `ifdef INST_CACHE
   .ic2memReqAddr_o      (ic2memReqAddr_o     ),      // memory read address
   .ic2memReqValid_o     (ic2memReqValid_o    ),     // memory read enable
+  .ic2memReqWay_o       (ic2memReqWay_o      ),
   .mem2icTag_i          (mem2icTag_i         ),          // tag of the incoming data
   .mem2icIndex_i        (mem2icIndex_i       ),        // index of the incoming data
   .mem2icData_i         (mem2icData_i        ),         // requested data
@@ -1608,6 +1612,7 @@ LSU lsu (
 
   .dc2memLdAddr_o       (dc2memLdAddr_o     ), // memory read address
   .dc2memLdValid_o      (dc2memLdValid_o    ), // memory read enable
+  .dc2memReqWay_o       (dc2memReqWay_o     ),
 
   .mem2dcLdTag_i        (mem2dcLdTag_i      ), // tag of the incoming datadetermine
   .mem2dcLdIndex_i      (mem2dcLdIndex_i    ), // index of the incoming data
@@ -1621,7 +1626,7 @@ LSU lsu (
 
   .mem2dcInv_i,     // dcache invalidation
   .mem2dcInvInd_i,  // dcache invalidation index
-  .mem2dcInvWay_i,  // dcache invalidation way (unusedndex
+  .mem2dcInvWay_i     	(mem2dcInvWay_i		),
 
   .mem2dcStComplete_i   (mem2dcStComplete_i ),
   .mem2dcStStall_i      (mem2dcStStall_i    ),