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chisel decoder. #2

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chisel decoder. #2

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0281c8f
switch to decoder, recode InstructionType uop to OneHot, improve disp…
sequencer Nov 24, 2021
2d77a83
bump
sequencer Jan 3, 2022
5aa9a8e
Update libraries, improve buildfiles
carlosedp Jan 3, 2022
3f7d84e
bump
sequencer Jan 3, 2022
58e9569
Rebase and fix decode pattern
carlosedp Jan 3, 2022
9789ee4
Fix type with cast and some test cases
carlosedp Jan 3, 2022
753378b
Improve formatting
carlosedp Jan 4, 2022
d676295
Improve API using some unmerged PRs
carlosedp Jan 10, 2022
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4 changes: 1 addition & 3 deletions build.sbt
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Original file line number Diff line number Diff line change
Expand Up @@ -27,8 +27,7 @@ lazy val chiselv = (project in file("."))

// Default library versions
lazy val versions = new {
val chisel3 = "3.5.0-RC2"
// val firrtl = "1.5-SNAPSHOT"
val chisel3 = "3.5-SNAPSHOT"
val chiseltest = "0.5.0-RC2"
val scalatest = "3.2.10"
val organizeimports = "0.5.0"
Expand All @@ -43,7 +42,6 @@ libraryDependencies ++= Seq(
"org.scalatest" %% "scalatest" % versions.scalatest % "test",
"com.carlosedp" %% "scalautils" % versions.scalautils,
"com.lihaoyi" %% "os-lib" % versions.oslib
// "edu.berkeley.cs" %% "firrtl" % versions.firrtl // Force using SNAPSHOT until next RC is cut (memory synth)
)
ThisBuild / scalafixDependencies += "com.github.liancheng" %% "organize-imports" % versions.organizeimports
addCompilerPlugin(("edu.berkeley.cs" % "chisel3-plugin" % versions.chisel3).cross(CrossVersion.full))
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2 changes: 1 addition & 1 deletion src/main/scala/CPUSingleCycle.scala
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Expand Up @@ -39,7 +39,7 @@ class CPUSingleCycle(

// Instantiate and initialize the ALU
val ALU = Module(new ALU(bitWidth))
ALU.io.ALUPort.inst := ERR_INST
ALU.io.ALUPort.inst := ERR
ALU.io.ALUPort.a := 0.U
ALU.io.ALUPort.b := 0.U

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8 changes: 4 additions & 4 deletions src/main/scala/Constants.scala
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@@ -1,9 +1,9 @@
package chiselv

import chisel3.experimental.ChiselEnum
import chisel3.experimental.{ChiselEnum, ChiselEnum1H}

object Instruction extends ChiselEnum {
val ERR_INST,
val ERR,
// RV32I
ADD, ADDI, SUB, LUI, AUIPC, // Arithmetic
SLL, SLLI, SRL, SRLI, SRA, SRAI, // Shifts
Expand All @@ -20,6 +20,6 @@ object Instruction extends ChiselEnum {
= Value
}

object InstructionType extends ChiselEnum {
val IN_ERR, INST_R, INST_I, INST_S, INST_B, INST_U, INST_J, INST_Z = Value
object InstructionType extends ChiselEnum1H {
val INST_I, INST_S, INST_B, INST_U, INST_J, INST_Z, INST_R, IN_ERR = Value
}
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