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add yosys-plugins #645

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f1f282c
ql-qlf: qlf_k6n10f: bram: don't match BRAM18_TDP module
lpawelcz Mar 3, 2022
f7a5d47
ql-qlf: qlf_k6n10f: bram: rewrite BRAM36_TDP techmap
lpawelcz Mar 3, 2022
d84e8ed
ql-qlf: qlf_k6n10f: bram: use 4 port matching rules to enable TDP RAM…
lpawelcz Mar 3, 2022
f7ab627
ql-qlf: qlf_k6n10f: bram: introduce TDP synthesis test cases
lpawelcz Mar 3, 2022
9d61b87
tests: introduce post synthesis simulation infrastructure
lpawelcz Mar 4, 2022
e3cbd48
Merge pull request #264 from rakeshm75/update_cells_sim
mkurc-ant Mar 9, 2022
bf82038
ql-qlf: qlf_k6n10f: bram: add post synthesis simulation tests
lpawelcz Mar 4, 2022
2f7695e
ql-qlf: qlf_k6n10f: bram: techmap: rearrange ports
lpawelcz Mar 8, 2022
41084de
ql-qlf: qlf_k6n10f: bram: techmap: cleanup R/WMODES
lpawelcz Mar 9, 2022
97fbb80
ql-qlf: qlf_k6n10f: bram: techmap: switch RAM_ID from parameter to port
lpawelcz Mar 9, 2022
862ec6b
ql-qlf: qlf_k6n10f: bram: sim: switch RAM_ID from parameter to port
lpawelcz Mar 9, 2022
8dbda8d
Merge pull request #263 from antmicro/pcza/ql-qlf-k6n10f-tdp-inference
lpawelcz Mar 9, 2022
c093b65
Fixed minor bugs in k6n10f DSP model and techmap
mkurc-ant Mar 9, 2022
2e5d27f
Added equivalence checking tests for DSP multiplier and DSP SIMD infe…
mkurc-ant Mar 9, 2022
95ddca1
Fixed bugs in the k6n10f dsp_macc inference pass
mkurc-ant Mar 9, 2022
753b8be
Added equivalence check tests for k6n10f DSP MACC inference
mkurc-ant Mar 9, 2022
db952e9
Added installation of k6n10f simulation models that were missing
mkurc-ant Mar 10, 2022
d14b485
Merge pull request #266 from antmicro/k6n10f_dsp_tests
mkurc-ant Mar 10, 2022
af72a89
Merge pull request #267 from antmicro/k6n10f_install_files
mkurc-ant Mar 10, 2022
b48c605
Removed declaration of IdString variables as const members of the ql_…
mkurc-ant Mar 14, 2022
c87f7b0
Merge pull request #268 from antmicro/fix_idstring_consts
kgugala Mar 14, 2022
af9d4b2
update adder techmap to implement last 2 bits into regular logic
tpagarani Mar 15, 2022
5c7d58a
Merge pull request #269 from tpagarani/adder_map
mkurc-ant Mar 16, 2022
3494b2b
Add 'read_systemverilog' command
tgorochowik Mar 16, 2022
47c71ac
Force -parse flag for Surelog when reading Verilog directly
tgorochowik Mar 16, 2022
fb94f80
Merge pull request #270 from antmicro/read_systemverilog_alias
tgorochowik Mar 16, 2022
d849fd4
Merge pull request #272 from antmicro/verilog-via-uhdm-force-parse
tgorochowik Mar 16, 2022
3c89144
ql-qlf: qlf_k6n10f: bram: introduce BRAM36_SDP techmap
lpawelcz Mar 4, 2022
287027c
ql-qlf: qlf_k6n10f: bram: introduce BRAM36_SDP matching rules
lpawelcz Mar 4, 2022
f304150
ql-qlf: qlf_k6n10f: bram: add SDP simulation tests
lpawelcz Mar 7, 2022
32032bd
Merge pull request #271 from antmicro/pcza/ql-qlf-k6n10f-sdp-inference
lpawelcz Mar 17, 2022
27eb19f
fix the generation of carry chain for size <=2
tpagarani Mar 17, 2022
a2a80a1
Merge pull request #274 from tpagarani/adder_map
mkurc-ant Mar 17, 2022
29726c0
Rename the uhdm plugin to systemverilog
tgorochowik Mar 17, 2022
ee44dc6
ql-qlf: qlf_k6n10f: bram: modify matching rules
lpawelcz Mar 18, 2022
46810a5
Merge pull request #278 from antmicro/pcza/ql-qlf-k6n10f-tdp-matching…
lpawelcz Mar 21, 2022
5f26af3
Add a dummy uhdm plugin
tgorochowik Mar 23, 2022
50d463f
Update README
tgorochowik Mar 23, 2022
9852a6a
Merge pull request #276 from antmicro/rename-uhdm-plugin
tgorochowik Mar 23, 2022
0fba5f0
Traverse both allPackages and topPackages
Mar 15, 2022
4008242
Check for minimal int size
Mar 22, 2022
3327d62
Mark empty range as valid
Mar 18, 2022
91f7ff5
Merge pull request #279 from antmicro/parse-toppackage
rkapuscik Mar 23, 2022
7a42878
Handle vpiUnionVar
Mar 24, 2022
40a1431
Merge pull request #280 from antmicro/union-var
rkapuscik Mar 24, 2022
63a6f77
readme: s/SymbiFlow/F4PGA/
umarcor Mar 24, 2022
5c9f638
readme: remove redundant ToC; style
umarcor Mar 24, 2022
2cc5ef0
Merge pull request #281 from antmicro/umarcor/f4pga
kgugala Mar 28, 2022
2786a7a
Handle integer typespecs
Mar 29, 2022
f99d890
Handle vpiStringTypespec in parameters
Mar 29, 2022
474b430
Set initial state of all k6n10f DSP registers to zero.
mkurc-ant Mar 29, 2022
b3a8bb7
Replaced tabs with spaces.
mkurc-ant Mar 29, 2022
da27bc7
Headers cleanup
kgugala Mar 29, 2022
bef9e6f
Merge pull request #283 from antmicro/headers-cleanup
kgugala Mar 29, 2022
21c58a6
Merge pull request #282 from antmicro/k6n10f_dsp_ff_init
mkurc-ant Mar 29, 2022
22efa39
Updated expected test results
mkurc-ant Mar 21, 2022
9b0aa6a
Updated CI script to correctly report installed Yosys version
mkurc-ant Mar 21, 2022
d64a754
Merge pull request #277 from antmicro/fix_ql-qlf_adder_test
mkurc-ant Mar 30, 2022
e814089
Relicense to Apache-2.0
kgugala Mar 30, 2022
36aac32
Removed blocking assignments and reworked the assign statement for PP…
mkurc-ant Jan 26, 2022
c166cf2
Updated plugin test results
mkurc-ant Jan 26, 2022
01137e5
Merge pull request #204 from antmicro/pp3-fix-logic-model
mkurc-ant Apr 4, 2022
b26604b
Merge pull request #290 from antmicro/uhdm-handle-integer
rkapuscik Apr 4, 2022
10815d6
Merge pull request #285 from antmicro/apache-2.0
mithro Apr 4, 2022
70fb49c
systemverilog: visit_object only when debug or report flag
kamilrakoczy Apr 6, 2022
547947a
systemverilog: minor fixes
kamilrakoczy Apr 6, 2022
7bbc62f
Merge pull request #291 from antmicro/fix-visit-debug
kamilrakoczy Apr 6, 2022
98bf734
Make access to nexus-dsp_rules.txt in tests location indpenedent.
hzeller Apr 6, 2022
64ace45
Merge pull request #292 from hzeller/20220406-make-dsp-ff-test-locati…
mkurc-ant Apr 7, 2022
dcfdb90
Fix read_uhdm frontend
kamilrakoczy Apr 7, 2022
1256b0a
Merge pull request #294 from antmicro/fix-visit-debug
kamilrakoczy Apr 7, 2022
3de7485
Updated k6n10f DSP simulation model, techmaps and tests
mkurc-ant Apr 11, 2022
22b52fb
Fixed an issue with DSP signed multiplication. Added test.
mkurc-ant Apr 12, 2022
5b56a03
Aggregated all QL_DSP2 parameters into a single one named MODE_BITS
mkurc-ant Apr 12, 2022
5f4c089
Aggregated all BRAM parameters into a single MODE_BITS parameter.
mkurc-ant Apr 12, 2022
dce1529
Fixed incorrect acc_fir_i port width.
mkurc-ant Apr 13, 2022
8ae5bf7
Merge pull request #297 from antmicro/k6n10f_dsp_update
mkurc-ant Apr 13, 2022
fc678f9
Merge pull request #298 from antmicro/k6n10f_ram_dsp_mode_bits
mkurc-ant Apr 14, 2022
ccd5cc5
ql-qlf: update sim modules and techmaps
lpawelcz Mar 15, 2022
ca48b84
ql-qlf: k6n10f: bram: fix cell assertion in synthesis tests
lpawelcz Mar 16, 2022
25d228f
ql-qlf: k6n10f: tests: add 36bit fifo simulation test
lpawelcz Mar 17, 2022
43f41e3
Add README to UHDM plugin
tgorochowik Apr 14, 2022
91f6d3a
Add README for the SystemVerilog plugin
tgorochowik Apr 14, 2022
f0bdb13
Merge pull request #299 from antmicro/sv-readme
tgorochowik Apr 14, 2022
ff70a90
Merge pull request #275 from antmicro/pcza/ql-qlf-k6n10f-tdp-sim-update
mkurc-ant Apr 14, 2022
931a2f5
ql-qlf: sim: declare all ports with explicit net types
lpawelcz Apr 14, 2022
a4e48ee
systemverilog: abort when Surelog report error in design
kamilrakoczy Apr 14, 2022
6dc5a76
Merge pull request #301 from antmicro/abort-surelog-error
kamilrakoczy Apr 15, 2022
040b4fc
Add handling of primitive gates
Apr 15, 2022
d09ffc1
Merge pull request #302 from antmicro/handle-primitives
rkapuscik Apr 15, 2022
c6f745a
Add -parse-only flag
kamilrakoczy Apr 19, 2022
55c26d7
Merge pull request #304 from antmicro/add-parse-only
kamilrakoczy Apr 20, 2022
a667feb
Added support for overriding plugin installation path via the DESTDIR…
mkurc-ant Apr 22, 2022
8683b30
systemverilog: add dedicated wildcard operator errors
tgorochowik Apr 22, 2022
e79caaa
systemverilog: move object to argument to avoid code duplication
tgorochowik Apr 25, 2022
0434b84
Merge pull request #308 from antmicro/unknown_operators
tgorochowik Apr 25, 2022
94f8157
systemverilog: Add warnings to post inc/dec operations
tgorochowik Apr 22, 2022
f002d12
Merge pull request #307 from antmicro/post-ops-warnings
tgorochowik Apr 25, 2022
c19f808
Merge pull request #300 from antmicro/pcza/ql-qlf-k6n10f-default-net-…
mkurc-ant Apr 28, 2022
de65f96
Check for empty string when creating wiretype
Apr 14, 2022
5832347
Update import_typespec case
Apr 20, 2022
ca67fc1
Handle shortint and time typespecs
Apr 20, 2022
d27ab17
Fix packed ranges access in nets
Apr 20, 2022
faad973
Fix packed ranges access in array nets
Apr 25, 2022
192bef0
Use make_range for typespecs
Apr 27, 2022
84e9d35
Add handling of case ... inside
May 2, 2022
4098e8b
Fix typespecs in array nets
May 2, 2022
f79f203
Merge pull request #305 from antmicro/bump-surelog
rkapuscik May 2, 2022
6d0752e
Improve mark_as_unsigned error message
tgorochowik May 4, 2022
e8ddbed
Merge pull request #310 from antmicro/mark_as_unsigned
tgorochowik May 4, 2022
33d4d0c
Use new Surelog/ include location.
hzeller Apr 27, 2022
cfd794b
Merge pull request #309 from hzeller/20220427-fix-compilation-hickups
rkapuscik May 5, 2022
e4fbf9d
Parse function definitions in GenScopes
May 9, 2022
d03af06
Fix formatting
May 9, 2022
00590be
Merge pull request #314 from antmicro/gen-local-func
rkapuscik May 9, 2022
e9ce130
Add byte typespec handling
May 9, 2022
8cda051
Update typespec sizes
May 9, 2022
3264c68
ql-qlf: qlf_k6n10f: bram: add custom bram pass
lpawelcz Mar 10, 2022
53a7f65
ql-qlf: qlf_k6n10f: bram: update TDP_BRAM18 techmap
lpawelcz Mar 30, 2022
92e36d8
ql-qlf: qlf_k6n10f: bram: add second techmap
lpawelcz Mar 30, 2022
8a2130b
ql-qlf: qlf_k6n10f: bram: add BRAM18_TDP matching rules
lpawelcz Mar 30, 2022
840a724
ql-qlf: qlf_k6n10f: bram: add 2x18K sim module
lpawelcz Mar 30, 2022
9fc4673
ql-qlf: qlf_k6n10f: bram: enable custom bram pass and final techmap
lpawelcz Mar 30, 2022
64c1452
ql-qlf: qlf_k6n10f: bram: add 2x18K split tests
lpawelcz Mar 30, 2022
b8a82b3
ql-qlf: qlf_k6n10f: bram: update TDP BRAM defs
lpawelcz Mar 31, 2022
008d4e3
ql-qlf: qlf_k6n10f: tests: bram: extend tdp and sdp test cases
lpawelcz Mar 31, 2022
dc78ceb
ql-qlf: qlf_k6n10f: bram: fix 9bit mode
lpawelcz May 11, 2022
33f27c9
ql-qlf: qlf_k6n10f: tests: bram: enable 9x12 test cases
lpawelcz Mar 31, 2022
dbd630a
Fix logic var ranges access
May 12, 2022
0308bdb
Add a TODO
May 12, 2022
bad008e
Merge pull request #315 from antmicro/update-typespecs
rkapuscik May 12, 2022
2fa356d
Merge pull request #319 from antmicro/function-ranges
rkapuscik May 12, 2022
aadd173
Merge pull request #306 from antmicro/install-destdir
tgorochowik May 13, 2022
1068317
Fix var creation in unnamed scope
May 17, 2022
485bf61
Add default UHDM install directory
May 18, 2022
14452cf
Merge pull request #322 from antmicro/fix-systemverilog-make
rkapuscik May 18, 2022
c04c83c
Makefile: fix DESTDIR handling
Xiretza May 18, 2022
fe7835b
fix(sdc): fix missing include of <iterator>
Xiretza May 18, 2022
6bc19ef
Merge pull request #286 from antmicro/pcza/ql-qlf-k6n10f-tdp-split
mkurc-ant May 20, 2022
49ae2a0
ql-qlf: k6n10f: dsp: add QL_DSP2_MULT cell types
lpawelcz May 4, 2022
301e64b
ql-qlf: k6n10f: dsp: add pass for new cells inference
lpawelcz May 12, 2022
65c546d
ql-qlf: k6n10f: dsp: fix ql-dsp-macc pass
lpawelcz May 16, 2022
0bccb70
ql-qlf: k6n10f: dsp: enable new pass in synthesis script and fixup tests
lpawelcz May 12, 2022
d74e0df
ql-qlf: k6n10f: dsp: mark ports not available in architecture file
lpawelcz May 16, 2022
5a74318
Merge pull request #324 from Xiretza/fix-missing-include
tmichalak May 20, 2022
e0a8112
Merge pull request #323 from Xiretza/fix-destdir
tgorochowik May 20, 2022
e6d33bc
Merge pull request #321 from antmicro/var-unnamed
tgorochowik May 20, 2022
f578ad5
Makefile: prepend to build flags to avoid ignoring environment
Xiretza Jan 22, 2021
57a8ccd
Add a simple smoke test for the systemverilog plugin.
hzeller May 20, 2022
f5565a6
IWYU - the sdc plugin was only including a fraction of the headers it…
hzeller May 20, 2022
b606e56
Disable benign warnings.
hzeller May 20, 2022
e934512
Merge pull request #329 from hzeller/20220520-iwyu
mithro May 21, 2022
fe8fe89
Merge pull request #330 from hzeller/20220520-disable-benign-warnings
mithro May 21, 2022
ccda2ee
fix(systemverilog): disable -Werror
Xiretza May 18, 2022
79df982
Handle shortint in parameters
May 23, 2022
1afeb8e
Merge pull request #318 from antmicro/pcza/dsp-modes
mkurc-ant May 24, 2022
db3b072
Merge pull request #332 from antmicro/short-int-param
rkapuscik May 25, 2022
855aedc
Merge pull request #325 from Xiretza/disable-werror
rkapuscik May 25, 2022
c6bc59e
Merge pull request #327 from Xiretza/prepend-to-build-flags
rkapuscik May 25, 2022
42881a4
ql-qlf: k6n10f: add support for SDP split BRAM
lpawelcz May 25, 2022
6da55bc
ql-qlf: k6n10f: add tests for SDP split BRAM
lpawelcz May 25, 2022
c155a3c
Merge pull request #328 from hzeller/20220405-add-simple-sv-plugin-test
hzeller May 25, 2022
0f72816
Merge pull request #337 from antmicro/pcza/ql-qlf-k6n10f-sdp-split
mkurc-ant May 30, 2022
4d987ef
Handle missing typespecs
May 31, 2022
d11a575
Merge pull request #342 from antmicro/missing-typespecs
rkapuscik May 31, 2022
3ff5daf
The UHDM Serializer leaks memory if not Purge()-ed, so call it after …
hzeller Jun 1, 2022
3e2fdc2
Merge pull request #343 from hzeller/20220531-purge-serializer
rkapuscik Jun 1, 2022
cf91762
Use fullSVMode in Surelog
Jun 14, 2022
8950ad8
ql-qlf: k6n10f: ql-bram-split: set INIT params only if those exist
lpawelcz Jun 14, 2022
cd05588
Merge pull request #348 from antmicro/pcza/fix-bram-split
mkurc-ant Jun 14, 2022
95c2016
Merge pull request #347 from antmicro/fullsvmode
rkapuscik Jun 14, 2022
2584fba
Fix missing 'break' in switch/case.
hzeller Jun 15, 2022
4c5cf16
Merge pull request #350 from hzeller/20220614-fix-missing-break
rkapuscik Jun 15, 2022
7a6e117
Force -Werror in CI
tgorochowik Jun 17, 2022
c11d60a
ql: remove unused variable
tgorochowik Jun 17, 2022
5bad0a0
ql: fix port name error log
tgorochowik Jun 17, 2022
b04621e
ql: remove some leftover code
tgorochowik Jun 17, 2022
d2af8ad
Merge pull request #353 from antmicro/werror
tgorochowik Jun 21, 2022
9190d53
Add default enum range
Jun 22, 2022
a928adf
Do not annotate base types for enums
Jun 22, 2022
1daf333
Propagate ranges to enum items
Jun 22, 2022
aa99327
Added missing handling of -run parameter to the synth_quicklogic pass
mkurc-ant Jun 7, 2022
8ad8d06
Enabled inference of sync. reset DFFs in Yosys flow
mkurc-ant Jun 7, 2022
f4bb47e
Cleaned DFF simulation models and techmaps, added sync. reset flip-fl…
mkurc-ant Jun 7, 2022
cbc6ed9
Fixed simulation model for sh_dff, added missing techmap for _SHREG_D…
mkurc-ant Jun 13, 2022
ea77252
Updated tests for sh_dff and regular flip-flops, disabled latchsr tes…
mkurc-ant Jun 13, 2022
16dabb0
Removed emission of dff/dffn and latch/latchn. Replaced those with sd…
mkurc-ant Jun 22, 2022
7376359
Revert "Check for minimal int size"
Jun 22, 2022
2a1cf5c
Code review fixes
Jun 24, 2022
5b7faa2
Merge pull request #355 from antmicro/enum-widths
rkapuscik Jun 24, 2022
ff19603
Merge pull request #346 from antmicro/k6n10f-sync-sr
mkurc-ant Jun 24, 2022
5fd3b46
Preserve clock for DSP in any of multiply-accumulate modes
mkurc-ant Jun 24, 2022
c9af547
Merge pull request #356 from antmicro/fix-dsp-chtype
mkurc-ant Jun 24, 2022
f8af8a5
Support `longint` typespec
kbieganski Jun 28, 2022
37b40cc
Support `break` and `continue`
kbieganski Jun 20, 2022
75df29e
Skip non-synthesizable objects (#243)
kamilrakoczy Jun 29, 2022
be4dd83
Use AST_TO_UNSIGNED for shift operations
Jun 24, 2022
1fa23bc
Do not clone substituted nodes
Jun 29, 2022
6bc9630
Merge pull request #359 from antmicro/shift-unsigned
rkapuscik Jun 30, 2022
0a3daaf
Re added regular D flip-flops and latches.
mkurc-ant Jul 1, 2022
a3be11f
Added option "-nosdff" to disable synchronous set/reset flip-flop inf…
mkurc-ant Jul 6, 2022
36ac139
Added tests for k6n10f synch/async S/R flip-flop inference
mkurc-ant Jul 6, 2022
d149693
Merge pull request #361 from antmicro/k6n10f-readd-dffs
mkurc-ant Jul 6, 2022
a1df203
ql-qlf: k6n10f: DSP: move dsp simulation models to separate file
lpawelcz Jul 1, 2022
93f2450
ql-qlf: k6n10f: DSP: adjust techmaps
lpawelcz Jul 6, 2022
29d9b06
ql-qlf: k6n10f: DSP: adjust custom passes
lpawelcz Jul 6, 2022
bb9f16a
ql-qlf: k6n10f: DSP: rework tests for 2 DSP flavors
lpawelcz Jul 6, 2022
89878d7
env: pin yosys version
acomodi Jul 8, 2022
8aa193b
Merge pull request #364 from antmicro/pin-yosys-version
acomodi Jul 8, 2022
568799a
ql-qlf: k6n10f: DSP: reintroduce feedback port
lpawelcz Jul 5, 2022
e585521
revert d74e0dff: ql-qlf: k6n10f: dsp: mark ports...
lpawelcz Jul 5, 2022
a54dfd4
ql-qlf: k6n10f: QL_DSP2_MULT: pass down acc_fir
lpawelcz Jul 6, 2022
d0c15e0
ql-qlf: k6n10f: QL_DSP2_MULTADD: remove port clk
lpawelcz Jul 6, 2022
51391e4
ql-qlf: k6n10f: DSP: pass down output_select and register_inputs conf…
lpawelcz Jul 11, 2022
23fa345
ql-qlf: k6n10f: DSP: add saturate_enable, shift_right and round ports…
lpawelcz Jul 11, 2022
9d3f0b6
Merge pull request #363 from antmicro/pcza/ql-qlf-k6n10f-dsp-extend
mkurc-ant Jul 11, 2022
4ce50aa
Remove unsupported -yydebug switch
May 26, 2022
f7857fc
Add separate compilation flow
May 26, 2022
03c1191
Add separate-compilation test
May 31, 2022
0bc0d89
Update plugin documentation
Jun 2, 2022
e0652c8
Check for separate compilation before annotating
Jul 1, 2022
55e4ac9
Pass extra_args unless linking UHDM
Jul 4, 2022
3bf2010
Update -link description
Jul 6, 2022
e71ace5
Merge pull request #344 from antmicro/separate-comp
rkapuscik Jul 12, 2022
f25bd03
Corrected detection if a QL_DSP2 can be MACC or MADD, updated the exi…
mkurc-ant Jul 18, 2022
2412f35
Added a test for type change of k6n10f QL_DSP2 in multiply+add mode.
mkurc-ant Jul 19, 2022
5c12d60
Code formatting
mkurc-ant Jul 19, 2022
582af47
Use a canonical way to test for an empty string.
hzeller Jul 19, 2022
52cdcc4
Merge pull request #369 from antmicro/fix-k6n10f-dsp-inference
mkurc-ant Jul 20, 2022
e714e59
Added "is_inferred" attribute to all inferred k6n10f DSPs to distingu…
mkurc-ant Jul 22, 2022
2f2f009
Remove unused modules from top_nodes
Jul 29, 2022
e17b791
Updated tests
mkurc-ant Jul 22, 2022
ae7a729
Code formatting
mkurc-ant Jul 29, 2022
3b3dcc5
Merge pull request #374 from antmicro/366-use-after-delete
rkapuscik Jul 29, 2022
7a69cd8
systemverilog: simplify unions
tgorochowik Aug 3, 2022
2a691f0
Merge pull request #375 from antmicro/simplify_unions
tgorochowik Aug 3, 2022
ebd8fa8
Merge pull request #370 from hzeller/20220719-use-canonical-empty-str…
tgorochowik Aug 3, 2022
8bb33fe
ql-qlf: k6n10f: add pass for inference of RAM with asymmetric port wi…
lpawelcz Apr 13, 2022
9ef6779
ql-qlf: k6n10f: enable pass for inference of RAM with asymmetric port…
lpawelcz May 2, 2022
f680e2a
ql-qlf: k6n10f: add tests for RAM with asymmetric port widths
lpawelcz May 2, 2022
65ac65e
Merge pull request #376 from antmicro/pcza/ql-qlf-k6n10f-asymmetric-ram
kgugala Aug 12, 2022
da93173
Merge pull request #373 from antmicro/k6n10f-manual-dsps
tmichalak Aug 16, 2022
766239d
Fixed the way BRAM wires are identified, ensured unique inferred BRAM…
mkurc-ant Aug 25, 2022
84beb50
Use port A of inferred BRAM only for writing and port B only for read…
mkurc-ant Aug 26, 2022
0713ed7
Merge pull request #379 from antmicro/fix-ql-asymmetric-bram-inference
mkurc-ant Aug 29, 2022
11d477e
Fix deprecated use of `which`
hzeller Sep 25, 2022
27208ce
Merge pull request #383 from hzeller/20220924-fix-use-of-which
kgugala Sep 26, 2022
24722f6
prepare to move into f4pga
umarcor Oct 3, 2022
b722212
add yosys-plugins
umarcor Oct 3, 2022
76d722a
merge upstream/main
umarcor Apr 25, 2023
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12 changes: 12 additions & 0 deletions .clang-format
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@@ -0,0 +1,12 @@
# Default Linux style
BasedOnStyle: LLVM
IndentWidth: 4
UseTab: Never
BreakBeforeBraces: Linux
AllowShortIfStatementsOnASingleLine: false
IndentCaseLabels: false

# From CodingReadme
TabWidth: 4
ContinuationIndentWidth: 2
ColumnLimit: 150
16 changes: 16 additions & 0 deletions .editorconfig
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@@ -0,0 +1,16 @@
# Editor config file, see http://editorconfig.org/
root = true

[*]
charset = utf-8
end_of_line = lf
insert_final_newline = true
trim_trailing_whitespace = true

[*.{h,cc,tcl}]
indent_style = space
indent_size = 4

[*.{v,sv}]
indent_style = space
indent_size = 2
12 changes: 11 additions & 1 deletion .gitattributes
Original file line number Diff line number Diff line change
@@ -1 +1,11 @@
/.gitcommit export-subst
/.gitcommit export-subst

# Settings to improve linguist data reporting (used by GitHub)
*.v linguist-language=Verilog
*.vh linguist-language=Verilog
*.sql linguist-language=SQL

third_party/** linguist-vendored

# FIXME: All vendor files should be under third_party
yosys-plugins/xdc/tests/minilitex_ddr_arty/** linguist-vendored
50 changes: 50 additions & 0 deletions .github/scripts/build-and-test.sh
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@@ -0,0 +1,50 @@
#! /bin/bash
# Copyright 2020-2022 F4PGA Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0

set -e

source .github/scripts/common.sh

##########################################################################

start_section Building

export CXXFLAGS=-Werror
make -C yosys-plugins UHDM_INSTALL_DIR=`pwd`/yosys-plugins/env/conda/envs/yosys-plugins/ plugins -j`nproc`
unset CXXFLAGS

end_section

##########################################################################

start_section Installing
make -C yosys-plugins install -j`nproc`
end_section

##########################################################################

start_section Testing
make -C yosys-plugins test -j`nproc`
end_section

##########################################################################

start_section Cleanup
make -C yosys-plugins plugins_clean -j`nproc`
end_section

##########################################################################
54 changes: 54 additions & 0 deletions .github/scripts/common.sh
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#! /bin/bash
# Copyright 2020-2022 F4PGA Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0

# Look for location binaries first
export PATH="$HOME/.local-bin/bin:$PATH"

# OS X specific common setup
if [[ "x${OS}" == "xmacOS" ]]; then
export PATH="/usr/local/opt/ccache/libexec:$PATH"
fi

# Parallel builds!
MAKEFLAGS="-j 2"

function action_fold() {
if [ "$1" = "start" ]; then
echo "::group::$2"
SECONDS=0
else
duration=$SECONDS
echo "::endgroup::"
printf "${GRAY}took $(($duration / 60)) min $(($duration % 60)) sec.${NC}\n"
fi
return 0;
}

function start_section() {
action_fold start "$1"
echo -e "${PURPLE}SymbiFlow Yosys Plugins${NC}: - $2${NC}"
echo -e "${GRAY}-------------------------------------------------------------------${NC}"
}

export -f start_section

function end_section() {
echo -e "${GRAY}-------------------------------------------------------------------${NC}"
action_fold end "$1"
}

export -f end_section
69 changes: 69 additions & 0 deletions .github/scripts/setup.sh
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@@ -0,0 +1,69 @@
#! /bin/bash
# Copyright 2020-2022 F4PGA Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0

set -e

source .github/scripts/common.sh

##########################################################################

# Output status information.
start_section Status
(
set +e
set -x
git status
git branch -v
git log -n 5 --graph
git log --format=oneline -n 20 --graph
)
end_section

##########################################################################

# Update submodules
start_section Submodules
(
git submodule update --init --recursive
)
end_section

##########################################################################

#Install yosys
start_section Install-Yosys
(
echo '================================='
echo 'Making env with Yosys and Surelog'
echo '================================='
make -C yosys-plugins env
source yosys-plugins/env/conda/bin/activate yosys-plugins
conda list
)
end_section

##########################################################################

start_section Yosys-Version
(
source yosys-plugins/env/conda/bin/activate yosys-plugins
echo $(which yosys)
echo $(which yosys-config)
echo $(yosys --version)
echo $(yosys-config --datdir)
)
end_section
66 changes: 66 additions & 0 deletions .github/workflows/Pipeline.yml
Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,13 @@ jobs:

- name: Check Licenses
uses: SymbiFlow/actions/checks@main
with:
exclude_license: |
./yosys-plugins/design_introspection/tests/selection_to_tcl_list/selection_to_tcl_list.v
./third_party/minilitex_ddr_arty/minilitex_ddr_arty.v
./third_party/VexRiscv_Lite/VexRiscv_Lite.v
#third_party: |
# ./third_party/googletest/


Format:
Expand Down Expand Up @@ -276,3 +283,62 @@ jobs:
run: |
PYTHONPATH=$(pwd) python3 -m f4pga
PYTHONPATH=$(pwd) python3 -m f4pga -h


Yosys-plugins:
name: 🔌 Plugins
runs-on: ubuntu-latest

steps:

- name: 🧰 Checkout
uses: actions/checkout@v3
with:
submodules: recursive

- name: 🐍 Setup Python
uses: actions/setup-python@v4

- name: 🔧 Install
run: |
sudo apt-get update
sudo apt-get install \
bison \
build-essential \
clang-format-8 \
cmake \
flex \
g++-9 \
gawk \
git \
graphviz \
libffi-dev \
libboost-system-dev \
libboost-python-dev \
libboost-filesystem-dev \
libreadline-dev \
pkg-config \
tcl-dev \
xdot \
zlib1g-dev

- name: Format
run: |
set -e
source .github/scripts/common.sh
make -C yosys-plugins format -j`nproc`
test $(git status --porcelain | wc -l) -eq 0 || { git diff; false; }

- name: ccache
uses: hendrikmuhs/ccache-action@v1

- name: 🔧 Install Yosys
run: |
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
source .github/scripts/setup.sh

- name: 🚧 Build and test plugins
run: |
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
source yosys-plugins/env/conda/bin/activate yosys-plugins
source .github/scripts/build-and-test.sh
7 changes: 7 additions & 0 deletions .gitignore
Original file line number Diff line number Diff line change
@@ -1,3 +1,10 @@
*.pyc
*.sw*
/f4pga/build/

*.d
*.o
*.so
*.swp
*.log
yosys-plugins/ql-qlf/pmgen/*
5 changes: 4 additions & 1 deletion .gitmodules
Original file line number Diff line number Diff line change
@@ -1,3 +1,6 @@
[submodule "third_party/make-env"]
path = third_party/make-env
url = https://github.com/SymbiFlow/make-env/
url = https://github.com/SymbiFlow/make-env
[submodule "third_party/googletest"]
path = third_party/googletest
url = https://github.com/google/googletest
21 changes: 21 additions & 0 deletions third_party/VexRiscv_Lite/LICENSE
Original file line number Diff line number Diff line change
@@ -0,0 +1,21 @@
MIT License

Copyright (c) 2016 Spinal HDL contributors

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
9 changes: 9 additions & 0 deletions third_party/VexRiscv_Lite/README.yosys-symbiflow-plugins
Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
Name: This repository hosts a RISC-V implementation written in SpinalHDL.
Short Name: VexRiscv
URL: https://github.com/SpinalHDL/VexRiscv
Version: 0
Date: 16/06/2019
License: MIT License

Description:
This package is used as stimuli in some test cases that verify that the Yosys plugins produce expected results.
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