remove unused code

clash-lang · Mar 7, 2024 · 9c4ad84 · 9c4ad84
1 parent 3bd03de
commit 9c4ad84
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diff --git a/clash-vexriscv/Makefile b/clash-vexriscv/Makefile
@@ -22,8 +22,6 @@ clean:
 $(CPU_DIR)/VexRiscv.v: $(CPU_DIR)/src/main/scala/example/ExampleCpu.scala
 	cd $(CPU_DIR); sbt "runMain example.ExampleCpu"
 	cd $(CPU_DIR); sed -i -E '/\/\/ Git hash  :.*$$/d' VexRiscv.v
-	# cd $(CPU_DIR); sed -i 's/module VexRiscv/module VexRiscvInner/g' VexRiscv.v
-	# cd $(CPU_DIR); cat ../example-cpu/VexRiscvWrapped.v >> VexRiscv.v
 
 $(OUT_DIR)/VexRiscv.v: $(CPU_DIR)/VexRiscv.v
 	mkdir -p $(OUT_DIR)

diff --git a/clash-vexriscv/src/VexRiscv/JtagTcpBridgeHaskell.hs b/clash-vexriscv/src/VexRiscv/JtagTcpBridgeHaskell.hs
diff --git a/clash-vexriscv/src/ffi/impl.cpp b/clash-vexriscv/src/ffi/impl.cpp
@@ -27,8 +27,6 @@ typedef struct {
 	int32_t rx_buffer_size;
 	int32_t rx_buffer_remaining;
 	JTAG_INPUT prev_input;
-
-	uint64_t tck_change_counter;
 } vexr_jtag_bridge_data;
 
 extern "C" {
@@ -172,8 +170,6 @@ vexr_jtag_bridge_data *vexr_jtag_bridge_init(uint16_t port)
 
 	d->prev_input = { 0, 0, 0 };
 
-	d->tck_change_counter = 0;
-
 	d->timer = 0;
 	d->self_sleep = 0;
 	d->check_new_connections_timer = 0;
@@ -214,7 +210,6 @@ vexr_jtag_bridge_data *vexr_jtag_bridge_init(uint16_t port)
 
 void vexr_jtag_bridge_step(vexr_jtag_bridge_data *d, const JTAG_OUTPUT *output, JTAG_INPUT *input)
 {
-	const int WAIT_PERIOD = 83333;
 	// We set the input values to their last here
 	// so that only the "successful" path has to update them
 
@@ -273,19 +268,6 @@ void vexr_jtag_bridge_step(vexr_jtag_bridge_data *d, const JTAG_OUTPUT *output,
 			input->tdi = (buffer & 2) != 0;
 			input->tck = (buffer & 8) != 0;
 
-			// printf("\n[JTAG_BRIDGE] ");
-			// printf("%d %d %d %d\n",
-			// 	d->tck_change_counter,
-			// 	input->jtag_TCK,
-			// 	input->jtag_TMS,
-			// 	input->jtag_TDI
-			// );
-
-			if (input->tck != d->prev_input.tck) {
-				d->tck_change_counter++;
-			}
-
-
 
 			d->prev_input = *input;
 			if(buffer & 4){