Merge pull request #173 from efabless/gf180_add_checks

Gf180 add checks

check_manager/__init__.py

@@ -114,7 +114,7 @@ def run(self):
 class GpioDefines(CheckManager):
     __ref__ = 'gpio_defines'
     __surname__ = 'GPIO-Defines'
-    __supported_pdks__ = ['sky130A', 'sky130B']
+    __supported_pdks__ = ['gf180mcuC','sky130A', 'sky130B']
 
     def __init__(self, precheck_config, project_config):
         super().__init__(precheck_config, project_config)
@@ -124,7 +124,8 @@ def run(self):
                                               output_directory=self.precheck_config['output_directory'],
                                               project_type=self.project_config['type'],
                                               user_defines_v=Path("verilog/rtl/user_defines.v"),
-                                              include_extras=[])
+                                              include_extras=[],
+                                              precheck_config=self.precheck_config)
         if self.result:
             logging.info("{{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid.")
         else:
@@ -190,11 +191,14 @@ def __init__(self, precheck_config, project_config):
 class KlayoutMetalMinimumClearAreaDensity(KlayoutDRC):
     __ref__ = 'klayout_met_min_ca_density'
     __surname__ = 'Klayout Metal Minimum Clear Area Density'
-    __supported_pdks__ = ['sky130A', 'sky130B']
+    __supported_pdks__ = ['gf180mcuC','sky130A', 'sky130B']
 
     def __init__(self, precheck_config, project_config):
         super().__init__(precheck_config, project_config)
-        self.drc_script_path = Path(__file__).parent.parent / "checks/drc_checks/klayout/met_min_ca_density.lydrc"
+        if 'gf180mcu' in precheck_config['pdk_path'].stem:
+            self.drc_script_path = Path(__file__).parent.parent / "checks/drc_checks/klayout/gf180mcu_density.lydrc"
+        else:
+            self.drc_script_path = Path(__file__).parent.parent / "checks/drc_checks/klayout/met_min_ca_density.lydrc"
 
 
 class KlayoutOffgrid(KlayoutDRC):
@@ -348,21 +352,27 @@ def run(self):
 class XOR(CheckManager):
     __ref__ = 'xor'
     __surname__ = 'XOR'
-    __supported_pdks__ = ['sky130A', 'sky130B']
+    __supported_pdks__ = ['gf180mcuC', 'sky130A', 'sky130B']
 
     def __init__(self, precheck_config, project_config):
         super().__init__(precheck_config, project_config)
 
     def run(self):
         # TODO(nofal): This should be a single file across the entire precheck
-        magicrc_file_path = self.precheck_config['pdk_path'] / f"libs.tech/magic/{self.precheck_config['pdk_path'].name}.magicrc"
-        gds_golden_wrapper_file_path = self.precheck_config['caravel_root'] / f"gds/{self.project_config['golden_wrapper']}.gds"
+
+        if 'gf180mcu' in self.precheck_config['pdk_path'].stem:
+            magicrc_file_path = self.precheck_config['pdk_path'] / f"libs.tech/magic/{self.precheck_config['pdk_path'].name}.magicrc"
+            gds_golden_wrapper_file_path = Path(__file__).parent.parent / "_default_content/gds/user_project_wrapper_empty_gf180mcu.gds"
+        else:
+            magicrc_file_path = self.precheck_config['pdk_path'] / f"libs.tech/magic/{self.precheck_config['pdk_path'].name}.magicrc"
+            gds_golden_wrapper_file_path = self.precheck_config['caravel_root'] / f"gds/{self.project_config['golden_wrapper']}.gds"
 
         self.result = xor_check.gds_xor_check(self.precheck_config['input_directory'],
                                               self.precheck_config['output_directory'],
                                               magicrc_file_path,
                                               gds_golden_wrapper_file_path,
-                                              self.project_config)
+                                              self.project_config,
+                                              self.precheck_config)
         if self.result:
             logging.info("{{XOR CHECK PASSED}} The GDS file has no XOR violations.")
         else:

checks/drc_checks/klayout/gf180mcu_density.lydrc

@@ -0,0 +1,42 @@
+<?xml version="1.0" encoding="utf-8"?>
+<klayout-macro>
+ <description/>
+ <version/>
+ <category>drc</category>
+ <prolog/>
+ <epilog/>
+ <doc/>
+ <autorun>false</autorun>
+ <autorun-early>false</autorun-early>
+ <shortcut/>
+ <show-in-menu>true</show-in-menu>
+ <group-name>drc_scripts</group-name>
+ <menu-path>tools_menu.drc.end</menu-path>
+ <interpreter>dsl</interpreter>
+ <dsl-interpreter-name>drc-dsl-xml</dsl-interpreter-name>
+ <text>
+
+source($input, $top_cell)
+report("Density Checks", $report)
+
+verbose(true)
+
+deep
+
+comp_layer = "22/0"
+comp_dummy_layer = "22/4"
+
+# ---------------
+
+chip_boundary = input(235,4)
+#area = (m4+m4fill).area
+full_area = chip_boundary.area
+
+comp_density = polygons(comp_layer, comp_dummy_layer).area / full_area
+log("comp_density is #{comp_density}")
+if comp_density &gt; 0.7
+     chip_boundary.output("comp.density", "0.7 max comp density")
+end
+
+</text>
+</klayout-macro>

checks/gpio_defines_check/gpio_defines_check.py

@@ -44,7 +44,6 @@
 # Choosen illegal value for `USER_CONFIG_GPIO_<int>_INIT directives.
 VAL_ILLEGAL = "13'hXXXX"  # consistent with, in gpio_modes_base.v : `define GPIO_MODE_INVALID 13'hXXXX
 VAL_ILLEGAL_CF = VAL_ILLEGAL.casefold()
-LEGALREX = re.compile("^13'[hH][0-9a-fA-F]+$")  # matches a 'good' 13-bit hex-literal (no X's)
 
 # compile REX just once.
 MODREX = re.compile("^__gpioModeObserve[0-9]+$")
@@ -61,8 +60,15 @@ def main(*args, **kwargs):
     project_type = kwargs["project_type"]
     user_defines_v = kwargs["user_defines_v"]
     include_extras_v = kwargs["include_extras"]
+    precheck_config =  kwargs["precheck_config"]
     errs = 0
 
+    if 'gf180mcu' in precheck_config['pdk_path'].stem:
+        LEGALREX = re.compile("^10'[hH][0-9a-fA-F]+$")  # matches a 'good' 10-bit hex-literal (no X's)
+    else:
+        LEGALREX = re.compile("^13'[hH][0-9a-fA-F]+$")  # matches a 'good' 13-bit hex-literal (no X's)
+
+
     gpio_defines_report = output_directory / 'outputs/reports/gpio_defines.report'
 
     # for includes_extras_v & user_defines_v: if relative: make absolute RELATIVE TO INPUT_DIRECTORY (user project root)