Fully update for HEEPsilon (#27)

* fixes on sw for interleaved memory * revendor x-heep * Update esl_epfl_x_heep to esl-epfl/x-heep@76d58ef Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 76d58efe7b9dec0723c1cb9aaf8ad76ad6c85373 * Update ci (esl-epfl/x-heep#454) (Luigi Giuffrida) * fix num of FPGAs in README (Davide Schiavone) * Porting Ultrascale ZCU104 board (esl-epfl/x-heep#435) (jmiranda) * Add absolute path to `CMakeLists.txt` match statements (esl- epfl/x-heep#469) (Michele Caon) * add SystemC example (esl-epfl/x-heep#443) (Davide Schiavone) * Structs multireg fix (esl-epfl/x-heep#466) (Stefano Albini) * add Coremark and update cv32e40p (esl-epfl/x-heep#465) (Davide Schiavone) * add tiled matmul (esl-epfl/x-heep#464) (Davide Schiavone) * fix software errors/warnings (esl-epfl/x-heep#462) (Davide Schiavone) * add xcelium support (esl-epfl/x-heep#452) (Davide Schiavone) * Add matmul example (esl-epfl/x-heep#461) (Davide Schiavone) * fix typo in debug_ss (esl-epfl/x-heep#460) (Luigi Giuffrida) * update riscv_dbg (esl-epfl/x-heep#230) (Davide Schiavone) * Fix esl-epfl/x-heep#430 (esl-epfl/x-heep#459) (David Mallasén Quintana) * fix esl-epfl/x-heep#447 (esl-epfl/x-heep#453) (Davide Schiavone) * fix typo (esl-epfl/x-heep#458) (Luigi Giuffrida) * add OpenOCD BSCAN configuration file (esl-epfl/x-heep#457) (Luis Waucquez) * Removed repeated code in dma hal (esl-epfl/x-heep#456) (Juan-n-only) * Fix linker script generation (esl-epfl/x-heep#451) (Luigi Giuffrida) * Add a target to the Makefile to directly program the FPGA (esl- epfl/x-heep#450) (Luigi Giuffrida) * [hw/sw] update flash load linker script, data_interleaved and data_flash_only sections (esl-epfl/x-heep#399) (Davide Schiavone) * add simple accelerator example (esl-epfl/x-heep#446) (Davide Schiavone) * change python format for Bootrom (esl-epfl/x-heep#442) (Davide Schiavone) * fix memset bug (esl-epfl/x-heep#439) (Mattia Consani) * update cv32e40px with dual-read support (esl-epfl/x-heep#441) (Davide Schiavone) * Added X-HEEP Reference. (esl-epfl/x-heep#440) (Simone Machetti) * add w25q128 flash BSP (esl-epfl/x-heep#433) (Mattia Consani) * removed FEMU (esl-epfl/x-heep#437) (Simone Machetti) * update cve2 (esl-epfl/x-heep#284) (Davide Schiavone) * porting X-HEEP to the nexys FPGA (esl-epfl/x-heep#432) (Davide Schiavone) * Add standard and quad write functionality to flash model (esl- epfl/x-heep#426) (Mattia Consani) * revert 🐛 introduced in last revendor of iceprog (davide schiavone) * Add `example_spi_host_quadIO` (esl-epfl/x-heep#401) (Mattia Consani) * fix minimal cfg with stack and heap size (esl-epfl/x-heep#431) (Davide Schiavone) * Update verible url (esl-epfl/x-heep#428) (David Mallasén Quintana) * expose DMA slots externally + external FIFO example (esl- epfl/x-heep#417) (grinningmosfet) * Updated the documentation on how to add external interrupts (esl- epfl/x-heep#427) (Juan-n-only) * add citation in readme (Davide Schiavone) * Fix run-blinky-freertos command (esl-epfl/x-heep#424) (jmiranda) * Compilation fix (esl-epfl/x-heep#422) (jmiranda) * add stack and heap size as parameters to mcu-gen (esl- epfl/x-heep#419) (Luigi Giuffrida) Signed-off-by: mbelda <[email protected]> * revendor x-heep Luigi fix * Update esl_epfl_x_heep to LuigiGiuffrida98/x-heep@849539d Update code from upstream repository https://github.com/Luigi2898/x-heep.git to revision 849539ddf996926f9b679837f3bc84c0799287bb Signed-off-by: mbelda <[email protected]> * 1. Port ZCU / 2. fix xdc file for the ZCU / 3. Fix top to include dif clk for ZCU * added new pin and constraint files * removed vendor modification * Add matmul example * Add matmul os example * Add transformer example * add transformer example * reduced transformer example * adapt minimal cfg for the cgra * revendorizing oe-cgra * revendorizing x-heep * fix makefile and .core files * Fixing .core for heepsilon * Fixing .core for heepsilon: adding parameters * Fixing .core for heepsilon: adding parameters v2 * Update .core and xheep vendor * Re-vendorizing x-heep to last commit * Updating HEEPsilon to the final version, plus fixing CGRA memory generation conflicts (generate_sram_...tcl(s)) * deleting fpga xheep link --------- Signed-off-by: mbelda <[email protected]> Co-authored-by: mbelda <[email protected]> Co-authored-by: Miranda Calero José Angel <[email protected]>
esl-epfl · Oct 8, 2024 · bfab89e · bfab89e
1 parent b55b14f
commit bfab89e
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Showing 597 changed files with 57,344 additions and 23,075 deletions.
diff --git a/Makefile b/Makefile
@@ -13,12 +13,11 @@ PORT		?= /dev/ttyUSB2
 
 # 1 external domain for the CGRA
 EXTERNAL_DOMAINS = 1
-# Use more memory banks
-MEMORY_BANKS = 4
-
-# Project options are based on the app to be build (default - hello_world)
-PROJECT  ?= hello_world
+PROJECT ?= hello_world
 
+#MEMORY_BANKS ?= 2 # Multiple of 2
+#MEMORY_BANKS_IL ?= 4 # Power of 2
+
 export HEEP_DIR = hw/vendor/esl_epfl_x_heep/
 include $(HEEP_DIR)Makefile.venv
 
@@ -37,8 +36,6 @@ heepsilon-gen:
 # This is needed to be done after the X-HEEP mcu-gen because the test-bench to be used is the one from heepsilon, not the one from X-HEEP.
 mcu-gen: heepsilon-gen
 	$(MAKE) -f $(XHEEP_MAKE) EXTERNAL_DOMAINS=${EXTERNAL_DOMAINS} MEMORY_BANKS=${MEMORY_BANKS} $(MAKECMDGOALS)
-	cd hw/vendor/esl_epfl_x_heep &&\
-	$(PYTHON) util/mcu_gen.py --cfg mcu_cfg.hjson --pads_cfg pad_cfg.hjson  --outdir ../../../tb/ --memorybanks $(MEMORY_BANKS) --tpl-sv ../../../tb/tb_util.svh.tpl
 
 ## Builds (synthesis and implementation) the bitstream for the FPGA version using Vivado
 ## @param FPGA_BOARD=nexys-a7-100t,pynq-z2

diff --git a/heepsilon.core b/heepsilon.core
@@ -97,25 +97,26 @@ filesets:
     file_type: systemVerilogSource
 
   rtl-fpga:
+    depend:
+    - openhwgroup.org:systems:core-v-mini-mcu-fpga
     files:
-    - hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv
-    - hw/fpga/sram_wrapper.sv
-    - hw/fpga_cgra/cgra_sram_wrapper.sv
-    - hw/fpga_cgra/cgra_clock_gate.sv
-    - hw/fpga_cgra/xilinx_heepsilon_wrapper.sv
-    file_type: systemVerilogSource
+    - hw/fpga_cgra/scripts/generate_sram_general.tcl: { file_type: tclSource }
+    - hw/fpga_cgra/scripts/generate_sram_emem.tcl: { file_type: tclSource }
+    - hw/vendor/esl_epfl_x_heep/hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv:  { file_type: systemVerilogSource }
+    - hw/fpga_cgra/cgra_sram_wrapper.sv:  { file_type: systemVerilogSource }
+    - hw/fpga_cgra/cgra_clock_gate.sv:  { file_type: systemVerilogSource }
+    - hw/fpga_cgra/xilinx_heepsilon_wrapper.sv:  { file_type: systemVerilogSource }
 
-  ip-fpga:
+  xdc-fpga-pynq-z2:
     files:
-    - hw/fpga/scripts/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
-    - hw/fpga/scripts/generate_sram.tcl:  { file_type: tclSource }
-    - hw/fpga/prim_xilinx_clk.sv:  { file_type: systemVerilogSource } # Here there are the following modules
-    - hw/fpga/cve2_xilinx_clock_gate.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_input_xilinx.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_output_xilinx.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_inout_xilinx.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_bypass_input_xilinx.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_bypass_output_xilinx.sv:  { file_type: systemVerilogSource }
+    - hw/fpga_cgra/constraints/pynq-z2/pin_assign.xdc
+    - hw/fpga/constraints/pynq-z2/constraints.xdc
+    file_type: xdc
+
+  xdc-fpga-zcu104:
+    files:
+    - hw/fpga_cgra/constraints/zcu104/pin_assign.xdc
+    file_type: xdc
 
   fpga-arm-emulation:
     depend:
@@ -127,33 +128,71 @@ filesets:
     - linux_femu/constraints/pin_assign.xdc: {file_type: xdc}
     - linux_femu/constraints/constraints.xdc: {file_type: xdc}
 
-  xdc-fpga-pynq-z2:
-    files:
-    - hw/fpga_cgra/constraints/pin_assign.xdc
-    file_type: xdc
-
-  netlist-fpga:
-    files:
-    - build/openhwgroup.org_systems_core-v-mini-mcu_0/nexys-a7-100t-vivado/core_v_mini_mcu_xiling_postsynth.v
-    file_type: verilogSource
-
 parameters:
   COREV_PULP:
     datatype: int
     paramtype: vlogparam
+    description: |
+      Enables COREV_PULP custom RISC-V extension on the CV32E40P core. Admitted values: 1|0.
+    default: 0
+  FPU:
+    datatype: int
+    paramtype: vlogparam
+    description: |
+      Enables RV32F RISC-V extension on the CV32E40P core. Admitted values: 1|0.
     default: 0
   JTAG_DPI:
     datatype: int
     paramtype: vlogparam
+    description: |
+      Enables testbench JTAG DIPs. Admitted values: 1|0.
     default: 0
+  X_EXT:
+    datatype: int
+    paramtype: vlogparam
+    description: |
+      Enables CORE-V-XIF interface for the CV32E40X and CV32E40PX cores. Admitted values: 1|0.
+    default: 0
+  USE_EXTERNAL_DEVICE_EXAMPLE:
+    datatype: int
+    paramtype: vlogparam
+    description: |
+      Enables testbench modules compilation. Admitted values: 1|0.
+    default: 1
   USE_UPF:
     datatype: bool
     paramtype: vlogdefine
-    default: false
+    description: |
+      Enables simulation with UPF with Modelsim/VCS
+  REMOVE_OBI_FIFO:
+    datatype: bool
+    paramtype: vlogdefine
+    description: |
+      Remove the FIFO between the BUS and the peripherals subsystems
   SYNTHESIS:
     datatype: bool
     paramtype: vlogdefine
     default: false
+  VERILATOR: #used by SV2V
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
+  SIM_SYSTEMC:
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
+  FPGA_SYNTHESIS:
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
+  FPGA_NEXYS:
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
+  FPGA_ZCU104:
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
   # Make the parameter known to FuseSoC to enable overrides from the
   # command line. If not overwritten, use the generic technology library.
   PRIM_DEFAULT_IMPL:
@@ -266,15 +305,43 @@ targets:
     description: TUL Pynq-Z2 Board
     filesets_append:
     - x_heep_system
-    - files_rtl_generic # Already added by default?
     - rtl-fpga
-    - ip-fpga
     - xdc-fpga-pynq-z2
     - ext_bus
     parameters:
-    - COREV_PULP=0
+    - COREV_PULP
+    - FPU
+    - X_EXT
     - SYNTHESIS=true
+    - REMOVE_OBI_FIFO
+    - FPGA_SYNTHESIS=true
     tools:
       vivado:
         part: xc7z020clg400-1
+        board_part: tul.com.tw:pynq-z2:part0:1.0
+        board_repo_paths: [../../../hw/fpga/board_files/vendor/esl_epfl_pynq_z2_board_files]
+    toplevel: [xilinx_heepsilon_wrapper]
+
+  zcu104:
+    <<: *default_target
+    default_tool: vivado
+    description: ZCU104 Evaluation Board
+    filesets_append:
+    - x_heep_system
+    - rtl-fpga
+    - xdc-fpga-zcu104
+    - ext_bus
+    parameters:
+    - COREV_PULP
+    - FPU
+    - X_EXT
+    - SYNTHESIS=true
+    - REMOVE_OBI_FIFO
+    - FPGA_SYNTHESIS=true
+    - FPGA_ZCU104=true
+    tools:
+      vivado:
+        part: xczu7ev-ffvc1156-2-e
+        board_part: xilinx.com:zcu104:part0:1.0
+        board_repo_paths: [../../../hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files]
     toplevel: [xilinx_heepsilon_wrapper]
diff --git a/hw/fpga b/hw/fpga
diff --git a/hw/fpga_cgra/cgra_sram_wrapper.sv b/hw/fpga_cgra/cgra_sram_wrapper.sv
@@ -16,25 +16,87 @@ module cgra_sram_wrapper #(
     input  logic [AddrWidth-1:0] addr_i,   // request address
     input  logic [         31:0] wdata_i,  // write data
     input  logic [          3:0] be_i,     // write byte enable
-    input  logic                 set_retentive_i,
+    input  logic                 set_retentive_ni,
     // output ports
     output logic [         31:0] rdata_o   // read data
 );
-  sram_wrapper#(
-    .NumWords (NumWords),
-    .DataWidth(DataWidth),
-    .AddrWidth(AddrWidth)
-  ) sram_wrapper_i(
-    .clk_i          (clk_i),
-    .rst_ni         (rst_ni),
-    .req_i          (req_i),
-    .we_i           (we_i),
-    .addr_i         (addr_i),
-    .wdata_i        (wdata_i),
-    .be_i           (be_i),
-    .set_retentive_ni(set_retentive_i),
-    // output ports
-    .rdata_o        (rdata_o)
-  );
+
+  localparam int unsigned NUM_WORDS = NumWords;
+
+  generate
+    if (NUM_WORDS == 128) begin
+      xilinx_emem_gen xilinx_sram_i (
+        .clka (clk_i),
+        .ena  (req_i),
+        .wea  ({4{req_i & we_i}} & be_i),
+        .addra(addr_i),
+        .dina (wdata_i),
+        // output ports
+        .douta(rdata_o)
+      );
+    end else if (NUM_WORDS == 512) begin
+      xilinx_mem_gen_2k xilinx_sram_i (
+        .clka (clk_i),
+        .ena  (req_i),
+        .wea  ({4{req_i & we_i}} & be_i),
+        .addra(addr_i),
+        .dina (wdata_i),
+        // output ports
+        .douta(rdata_o)
+      );
+    end else if (NUM_WORDS == 1024) begin
+      xilinx_mem_gen_4k xilinx_sram_i (
+        .clka (clk_i),
+        .ena  (req_i),
+        .wea  ({4{req_i & we_i}} & be_i),
+        .addra(addr_i),
+        .dina (wdata_i),
+        // output ports
+        .douta(rdata_o)
+      );
+    end else if (NUM_WORDS == 2048) begin
+      xilinx_mem_gen_8k xilinx_sram_i (
+        .clka (clk_i),
+        .ena  (req_i),
+        .wea  ({4{req_i & we_i}} & be_i),
+        .addra(addr_i),
+        .dina (wdata_i),
+        // output ports
+        .douta(rdata_o)
+      );
+    end else if (NUM_WORDS == 4096) begin
+      xilinx_mem_gen_16k xilinx_sram_i (
+        .clka (clk_i),
+        .ena  (req_i),
+        .wea  ({4{req_i & we_i}} & be_i),
+        .addra(addr_i),
+        .dina (wdata_i),
+        // output ports
+        .douta(rdata_o)
+      );
+    end else if (NUM_WORDS == 8192) begin
+      xilinx_mem_gen_32k xilinx_sram_i (
+        .clka (clk_i),
+        .ena  (req_i),
+        .wea  ({4{req_i & we_i}} & be_i),
+        .addra(addr_i),
+        .dina (wdata_i),
+        // output ports
+        .douta(rdata_o)
+      );
+    end else if (NUM_WORDS == 16384) begin
+      xilinx_mem_gen_64k xilinx_sram_i (
+        .clka (clk_i),
+        .ena  (req_i),
+        .wea  ({4{req_i & we_i}} & be_i),
+        .addra(addr_i),
+        .dina (wdata_i),
+        // output ports
+        .douta(rdata_o)
+      );
+    end else begin
+      $error("Bank size not generated for NumWords = %0d.", NumWords);
+    end
+  endgenerate
 
 endmodule
diff --git a/hw/fpga_cgra/constraints/pynq-z2/constraints.xdc b/hw/fpga_cgra/constraints/pynq-z2/constraints.xdc
@@ -0,0 +1 @@
+create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 5} [get_ports {clk_i}];
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 5} [get_ports {clk_i}];