Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add check on exec_ready_i to cv32e40x decode stage #368

Closed
wants to merge 1 commit into from
Closed
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 3 additions & 1 deletion hw/vendor/openhwgroup_cv32e40x/rtl/cv32e40x_id_stage.sv
Original file line number Diff line number Diff line change
Expand Up @@ -749,7 +749,9 @@ module cv32e40x_id_stage import cv32e40x_pkg::*;
// Also attempt to offload any CSR instruction. The validity of such instructions are only
// checked in the EX stage.
// Instructions with deassert_we set to 1 from the controller bypass logic will not be attempted offloaded.
assign xif_issue_if.issue_valid = instr_valid && (illegal_insn || csr_en) &&
// Only offload instructions if the EX stage is ready not to miss data from xif_issue.issue_resp
assign xif_issue_if.issue_valid = instr_valid && ex_ready_i &&
(illegal_insn || csr_en) &&
!(xif_accepted_q || xif_rejected_q || ctrl_byp_i.deassert_we);

// Keep xif_offloading_o high after an offloaded instruction was accepted or rejected to get
Expand Down
Original file line number Diff line number Diff line change
@@ -0,0 +1,15 @@
diff --git a/rtl/cv32e40x_id_stage.sv b/rtl/cv32e40x_id_stage.sv
index 1385dfb..11bc457 100644
--- a/rtl/cv32e40x_id_stage.sv
+++ b/rtl/cv32e40x_id_stage.sv
@@ -749,7 +749,9 @@ module cv32e40x_id_stage import cv32e40x_pkg::*;
// Also attempt to offload any CSR instruction. The validity of such instructions are only
// checked in the EX stage.
// Instructions with deassert_we set to 1 from the controller bypass logic will not be attempted offloaded.
- assign xif_issue_if.issue_valid = instr_valid && (illegal_insn || csr_en) &&
+ // Only offload instructions if the EX stage is ready not to miss data from xif_issue.issue_resp
+ assign xif_issue_if.issue_valid = instr_valid && ex_ready_i &&
+ (illegal_insn || csr_en) &&
!(xif_accepted_q || xif_rejected_q || ctrl_byp_i.deassert_we);

// Keep xif_offloading_o high after an offloaded instruction was accepted or rejected to get