Fix clk gating issue (patch) #584
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* Porting Ultrascale ZCU104 board (esl-epfl#435) Porting for Ultrascale * fix num of FPGAs in README * Update ci (esl-epfl#454) docker image integration plus CI update * Fix cmake error (esl-epfl#473) * Fix edit that breaks external applications * Fix MATCH string * Consider entire path when matching `PROJECT` as well - prevent build from failing if any part of the path includes `${PROJECT}` (e.g., the name of one of the applications. * Restrict regular expression on `main` as well --------- Co-authored-by: Michele Caon <[email protected]> --------- Co-authored-by: Davide Schiavone <[email protected]> Co-authored-by: Luigi Giuffrida <[email protected]> Co-authored-by: Michele Caon <[email protected]>
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@LuigiGiuffrida98 @davideschiavone this should be OK :) |
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@davideschiavone @LuigiGiuffrida98 this was verified in the FPGA, we can merge it |
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Fine for me. |
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// In Zynq7000, just bypass the clock gating because there are not enough BUFGs that can be
// cascaded with the BUFG of the MMCM.
// In the Zynq UltraScale+, it can be implemented as BUFGCE without trouble, since there
// are > 500 BUFGCEs and the rules for cascading are more relaxed.
// NOTE: This cannot be substituted by a latch+and