Add functionalities to flash bsp

.github/workflows/sim-apps-job/test_apps.py

@@ -24,7 +24,7 @@ class BColors:
 
 # Define parameters for the test_apps.py script
 SIMULATOR = "verilator"
-SIM_TIMEOUT_S = 600
+SIM_TIMEOUT_S = 600000
 LINKER = "on_chip"
 COMPILER = "gcc"
 
@@ -33,6 +33,40 @@ class BColors:
     "example_spi_read",
     "example_spidma_powergate",
     "example_spi_write",
+    "coremark",
+    "example_ams_peripheral",
+    "example_asm",
+    "example_cpp",
+    "example_data_processing_from_flash",
+    "example_dma",
+    "example_dma_2d",
+    "example_dma_external",
+    "example_dma_multichannel",
+    "example_dma_sdk",
+    "example_dma_subaddressing",
+    "example_ext_memory",
+    "example_fft",
+    "example_freertos_blinky",
+    "example_gpio_intr",
+    "example_gpio_toggle",
+    "example_i2s",
+    "example_iffifo",
+    "example_im2col",
+    "example_matadd",
+    "example_matadd_interleaved",
+    "example_matfadd",
+    "example_matmul",
+    "example_pdm2pcm",
+    "example_sdk_spi_flash",
+    "example_simple_accelerator",
+    "example_spi_read",
+    "example_spi_write",
+    "example_spidma_powergate",
+    "example_tensor_format_conv",
+    "example_timer_sdk",
+    "hello_world",
+    "memtest",
+    "minver"
 ]
 
 app_list = [app for app in os.listdir("sw/applications")]

core-v-mini-mcu.core

@@ -339,6 +339,7 @@ targets:
         vsim_options:
         - -sv_lib ../../../hw/vendor/lowrisc_opentitan/hw/dv/dpi/uartdpi/uartdpi
         - -sv_lib ../../../hw/vendor/pulp_platform_pulpissimo/rtl/tb/remote_bitbang/librbs
+        - -voptargs=+acc=npr
       vcs:
         vcs_options:
          - -override_timescale=1ns/1ps

hw/ip/dma/data/dma.hjson

@@ -186,12 +186,13 @@
       hwaccess: "hro",
       resval:        0,
       fields: [
-        { bits: "1:0", name: "MODE",
+        { bits: "2:0", name: "MODE",
           desc: "DMA operation mode",
           enum: [
             { value: "0", name: "LINEAR_MODE", desc: "Transfers data linearly"},
             { value: "1", name: "CIRCULAR_MODE", desc: "Transfers data in circular mode"},
             { value: "2", name: "ADDRESS_MODE" , desc: "Transfers data using as destination address the data from ADD_PTR"},
+            { value: "3", name: "SUBADDRESS_MODE" , desc: "Implements transferrin of data when SRC_PTR is fixed and related to a peripheral"},
           ]
         }
       ]

hw/ip/dma/rtl/dma.sv

@@ -105,15 +105,17 @@ module dma #(
   logic dma_window_intr_n;
 
   /* FIFO signals */
-  logic [Addr_Fifo_Depth-1:0] read_fifo_usage;
+  logic [3:0][Addr_Fifo_Depth-1:0] read_fifo_usage;
   logic [Addr_Fifo_Depth-1:0] read_addr_fifo_usage;
   logic [Addr_Fifo_Depth-1:0] write_fifo_usage;
 
   logic fifo_flush;
-  logic read_fifo_full;
-  logic read_fifo_empty;
+  logic [3:0] read_fifo_full;
+  logic [3:0] read_fifo_empty;
   logic read_fifo_alm_full;
-  logic read_fifo_pop;
+  logic read_fifo_pop_pad;
+  logic [3:0] read_fifo_pop;
+  logic [3:0] read_fifo_pop_act;
   logic [31:0] read_fifo_input;
   logic [31:0] read_fifo_output;
 
@@ -126,9 +128,11 @@ module dma #(
   logic write_fifo_empty;
   logic write_fifo_alm_full;
   logic write_fifo_push;
+  logic write_fifo_push_act;
   logic write_fifo_pop;
   logic [31:0] write_fifo_input;
   logic [31:0] write_fifo_output;
+  logic [31:0] write_fifo_input_act;
 
   /* Trigger signals */
   logic wait_for_rx;
@@ -151,8 +155,11 @@ module dma #(
   }
       dma_state_q, dma_state_d;
 
+  dma_data_type_t src_data_type;
+
   logic circular_mode;
   logic address_mode;
+  logic subaddressing_mode;
 
   logic dma_start_pending;
 
@@ -181,27 +188,88 @@ module dma #(
   assign clk_cg = clk_i & clk_gate_en_ni;
 `endif
 
+  fifo_v3 #(
+      .DEPTH(FIFO_DEPTH),
+      .FALL_THROUGH(1'b1),
+      .DATA_WIDTH(8)
+  ) dma_read_fifo_0_i (
+      .clk_i(clk_cg),
+      .rst_ni,
+      .flush_i(fifo_flush),
+      .testmode_i(1'b0),
+      // status flags
+      .full_o(read_fifo_full[0]),
+      .empty_o(read_fifo_empty[0]),
+      .usage_o(read_fifo_usage[0]),
+      // as long as the queue is not full we can push new data
+      .data_i(read_fifo_input[7:0]),
+      .push_i(data_in_rvalid),
+      // as long as the queue is not empty we can pop new elements
+      .data_o(read_fifo_output[7:0]),
+      .pop_i(read_fifo_pop_act[0])
+  );
 
+  fifo_v3 #(
+      .DEPTH(FIFO_DEPTH),
+      .FALL_THROUGH(1'b1),
+      .DATA_WIDTH(8)
+  ) dma_read_fifo_1_i (
+      .clk_i(clk_cg),
+      .rst_ni,
+      .flush_i(fifo_flush),
+      .testmode_i(1'b0),
+      // status flags
+      .full_o(read_fifo_full[1]),
+      .empty_o(read_fifo_empty[1]),
+      .usage_o(read_fifo_usage[1]),
+      // as long as the queue is not full we can push new data
+      .data_i(read_fifo_input[15:8]),
+      .push_i(data_in_rvalid),
+      // as long as the queue is not empty we can pop new elements
+      .data_o(read_fifo_output[15:8]),
+      .pop_i(read_fifo_pop_act[1])
+  );
 
-  /* Read FIFO */
   fifo_v3 #(
       .DEPTH(FIFO_DEPTH),
-      .FALL_THROUGH(1'b1)
-  ) dma_read_fifo_i (
+      .FALL_THROUGH(1'b1),
+      .DATA_WIDTH(8)
+  ) dma_read_fifo_2_i (
+      .clk_i(clk_cg),
+      .rst_ni,
+      .flush_i(fifo_flush),
+      .testmode_i(1'b0),
+      // status flags
+      .full_o(read_fifo_full[2]),
+      .empty_o(read_fifo_empty[2]),
+      .usage_o(read_fifo_usage[2]),
+      // as long as the queue is not full we can push new data
+      .data_i(read_fifo_input[23:16]),
+      .push_i(data_in_rvalid),
+      // as long as the queue is not empty we can pop new elements
+      .data_o(read_fifo_output[23:16]),
+      .pop_i(read_fifo_pop_act[2])
+  );
+
+  fifo_v3 #(
+      .DEPTH(FIFO_DEPTH),
+      .FALL_THROUGH(1'b1),
+      .DATA_WIDTH(8)
+  ) dma_read_fifo_3_i (
       .clk_i(clk_cg),
       .rst_ni,
       .flush_i(fifo_flush),
       .testmode_i(1'b0),
       // status flags
-      .full_o(read_fifo_full),
-      .empty_o(read_fifo_empty),
-      .usage_o(read_fifo_usage),
+      .full_o(read_fifo_full[3]),
+      .empty_o(read_fifo_empty[3]),
+      .usage_o(read_fifo_usage[3]),
       // as long as the queue is not full we can push new data
-      .data_i(read_fifo_input),
+      .data_i(read_fifo_input[31:24]),
       .push_i(data_in_rvalid),
       // as long as the queue is not empty we can pop new elements
-      .data_o(read_fifo_output),
-      .pop_i(read_fifo_pop)
+      .data_o(read_fifo_output[31:24]),
+      .pop_i(read_fifo_pop_act[3])
   );
 
   /* Read address mode FIFO */
@@ -239,8 +307,8 @@ module dma #(
       .empty_o(write_fifo_empty),
       .usage_o(write_fifo_usage),
       // as long as the queue is not full we can push new data
-      .data_i(write_fifo_input),
-      .push_i(write_fifo_push),
+      .data_i(write_fifo_input_act),
+      .push_i(write_fifo_push_act),
       // as long as the queue is not empty we can pop new elements
       .data_o(write_fifo_output),
       .pop_i(write_fifo_pop)
@@ -267,7 +335,7 @@ module dma #(
       .dma_start_i(dma_start),
       .dma_done_i(dma_done),
       .ext_dma_stop_i,
-      .read_fifo_full_i(read_fifo_full),
+      .read_fifo_full_i(|read_fifo_full),
       .read_fifo_alm_full_i(read_fifo_alm_full),
       .wait_for_rx_i(wait_for_rx),
       .data_in_gnt_i(data_in_gnt),
@@ -305,13 +373,13 @@ module dma #(
       .reg2hw_i(reg2hw),
       .dma_padding_fsm_on_i(dma_padding_fsm_on),
       .dma_start_i(dma_start),
-      .read_fifo_empty_i(read_fifo_empty),
+      .read_fifo_empty_i(&(read_fifo_empty)),
       .write_fifo_full_i(write_fifo_full),
       .write_fifo_alm_full_i(write_fifo_alm_full),
       .data_read_i(read_fifo_output),
       .padding_fsm_done_o(padding_fsm_done),
       .write_fifo_push_o(write_fifo_push),
-      .read_fifo_pop_o(read_fifo_pop),
+      .read_fifo_pop_o(read_fifo_pop_pad),
       .data_write_o(write_fifo_input)
   );
 
@@ -495,6 +563,117 @@ module dma #(
     end
   end
 
+  // Subaddressing mode controlling logic
+
+  always_ff @(posedge clk_cg, negedge rst_ni) begin
+    if (~rst_ni) begin
+      read_fifo_pop <= 4'b0000;
+    end else begin
+      if (subaddressing_mode == 1'b1) begin
+        case (src_data_type)
+          DMA_DATA_TYPE_HALF_WORD: begin
+
+            if (dma_start == 1'b1) begin
+              read_fifo_pop <= 4'b0011;
+            end else if (read_fifo_pop_pad == 1'b1) begin
+              if (read_fifo_pop == 4'b1100) begin
+                read_fifo_pop <= 4'b0011;
+              end else begin
+                read_fifo_pop <= read_fifo_pop << 2;
+              end
+            end
+          end
+
+          DMA_DATA_TYPE_BYTE: begin
+
+            if (dma_start == 1'b1) begin
+              read_fifo_pop <= 4'b0001;
+            end else if (read_fifo_pop_pad == 1'b1) begin
+              if (read_fifo_pop == 4'b1000) begin
+                read_fifo_pop <= 4'b0001;
+              end else begin
+                read_fifo_pop <= read_fifo_pop << 1;
+              end
+            end
+          end
+
+          default: read_fifo_pop <= {4{read_fifo_pop_pad}};
+
+        endcase
+      end else begin
+        read_fifo_pop <= {4{read_fifo_pop_pad}};
+      end
+    end
+  end
+
+  always_comb begin
+    if (subaddressing_mode == 1'b1) begin
+      if (read_fifo_pop_pad == 1'b1) begin
+        case (src_data_type)
+          DMA_DATA_TYPE_HALF_WORD: begin
+
+            read_fifo_pop_act = read_fifo_pop;
+
+            if (read_fifo_pop == 4'b0000) begin
+              write_fifo_input_act = '0;
+              write_fifo_push_act  = 1'b0;
+            end else if (read_fifo_pop == 4'b1100) begin
+              write_fifo_input_act = {{16{1'b0}}, write_fifo_input[31:16]};
+              write_fifo_push_act  = 1'b1;
+            end else if (read_fifo_pop == 4'b0011) begin
+              write_fifo_input_act = {{16{1'b0}}, write_fifo_input[15:0]};
+              write_fifo_push_act  = 1'b1;
+            end else begin
+              write_fifo_input_act = write_fifo_input;
+              write_fifo_push_act  = write_fifo_push;
+            end
+
+          end
+
+          DMA_DATA_TYPE_BYTE: begin
+
+            read_fifo_pop_act = read_fifo_pop;
+
+            if (read_fifo_pop == 4'b0000) begin
+              write_fifo_input_act = '0;
+              write_fifo_push_act  = 1'b0;
+            end else if (read_fifo_pop == 4'b1000) begin
+              write_fifo_input_act = {{24{1'b0}}, write_fifo_input[31:24]};
+              write_fifo_push_act  = 1'b1;
+            end else if (read_fifo_pop == 4'b0100) begin
+              write_fifo_input_act = {{24{1'b0}}, write_fifo_input[23:16]};
+              write_fifo_push_act  = 1'b1;
+            end else if (read_fifo_pop == 4'b0010) begin
+              write_fifo_input_act = {{24{1'b0}}, write_fifo_input[15:8]};
+              write_fifo_push_act  = 1'b1;
+            end else if (read_fifo_pop == 4'b0001) begin
+              write_fifo_input_act = {{24{1'b0}}, write_fifo_input[7:0]};
+              write_fifo_push_act  = 1'b1;
+            end else begin
+              write_fifo_input_act = write_fifo_input;
+              write_fifo_push_act  = write_fifo_push;
+            end
+
+          end
+
+          default: begin
+            write_fifo_input_act = write_fifo_input;
+            write_fifo_push_act = write_fifo_push;
+            read_fifo_pop_act = {4{read_fifo_pop_pad}};
+          end
+
+        endcase
+      end else begin
+        write_fifo_input_act = '0;
+        write_fifo_push_act = 1'b0;
+        read_fifo_pop_act = {4{read_fifo_pop_pad}};
+      end
+    end else begin
+      write_fifo_input_act = write_fifo_input;
+      write_fifo_push_act = write_fifo_push;
+      read_fifo_pop_act = {4{read_fifo_pop_pad}};
+    end
+  end
 
   /*_________________________________________________________________________________________________________________________________ */
 
@@ -550,11 +729,15 @@ module dma #(
 
   assign circular_mode = reg2hw.mode.q == 1;
   assign address_mode = reg2hw.mode.q == 2;
+  assign subaddressing_mode = reg2hw.mode.q == 4;
 
   assign wait_for_rx = |(reg2hw.slot.rx_trigger_slot.q[SLOT_NUM-1:0] & (~trigger_slot_i));
   assign wait_for_tx = |(reg2hw.slot.tx_trigger_slot.q[SLOT_NUM-1:0] & (~trigger_slot_i));
 
-  assign read_fifo_alm_full = (read_fifo_usage == LastFifoUsage[Addr_Fifo_Depth-1:0]);
+  assign read_fifo_alm_full = (read_fifo_usage[0] == LastFifoUsage[Addr_Fifo_Depth-1:0]) & 
+                              (read_fifo_usage[1] == LastFifoUsage[Addr_Fifo_Depth-1:0]) &
+                              (read_fifo_usage[2] == LastFifoUsage[Addr_Fifo_Depth-1:0]) &
+                              (read_fifo_usage[3] == LastFifoUsage[Addr_Fifo_Depth-1:0]);
   assign read_addr_fifo_alm_full = (read_addr_fifo_usage == LastFifoUsage[Addr_Fifo_Depth-1:0]);
   assign write_fifo_alm_full = (write_fifo_usage == LastFifoUsage[Addr_Fifo_Depth-1:0]);
 
@@ -563,4 +746,7 @@ module dma #(
   // Count gnt write transaction and generate event pulse if WINDOW_SIZE is reached
   assign dma_window_event = |reg2hw.window_size.q &  data_out_gnt & (window_counter + 'h1 >= {19'h0, reg2hw.window_size.q});
 
+
+  assign src_data_type = dma_data_type_t'(reg2hw.src_data_type.q);
+
 endmodule : dma