Added and integrated spi_obi_slave peripheral to x-heep

TARGET=sim

@@ -0,0 +1 @@
+$You are executing from: /home/fabian/Desktop/Bachelor_Project/x-heep

core-v-mini-mcu.core

@@ -36,6 +36,7 @@ filesets:
     - x-heep:ip:fast_intr_ctrl
     - x-heep:ip:obi_fifo
     - x-heep:ip:pdm2pcm
+    - x-heep:ip:obi_spi_slave
     files:
     - hw/core-v-mini-mcu/core_v_mini_mcu.sv
     - hw/core-v-mini-mcu/cpu_subsystem.sv
@@ -94,6 +95,7 @@ filesets:
     - hw/system/x_heep_system.vlt
     - hw/simulation/simulation.vlt
     - hw/ip/i2s/i2s.vlt
+    - hw/ip/obi_spi_slave/obi_spi_slave.vlt
     file_type: vlt
 
   rtl-fpga:
@@ -521,3 +523,4 @@ targets:
       openroad:
         flow_path: flow/OpenROAD-flow-scripts/flow
         make_target: synth
+

hw/core-v-mini-mcu/ao_peripheral_subsystem.sv

@@ -47,6 +47,27 @@ module ao_peripheral_subsystem
 
     output logic spi_flash_intr_event_o,
 
+
+    //SPI Slave
+    output logic spi_slave_sck_o,
+    input  logic spi_slave_sck_i,
+    output logic spi_slave_sck_oe_o,
+    output logic spi_slave_cs_o,
+    input  logic spi_slave_cs_i,
+    output logic spi_slave_cs_oe_o,
+    output logic spi_slave_miso_o,
+    input  logic spi_slave_miso_i,
+    output logic spi_slave_miso_oe_o,
+    output logic spi_slave_mosi_o,
+    input  logic spi_slave_mosi_i,
+    output logic spi_slave_mosi_oe_o,
+
+    //OBI master cpu subsystem:
+
+    // Instruction memory interface
+    output obi_req_t  spi_slave_req_o,
+    input  obi_resp_t spi_slave_resp_i,
+
     // POWER MANAGER
     input logic [31:0] intr_i,
     input logic [NEXT_INT_RND-1:0] intr_vector_ext_i,
@@ -482,4 +503,33 @@ module ao_peripheral_subsystem
       .intr_rx_parity_err_o(uart_intr_rx_parity_err_o)
   );
 
+
+  obi_spi_slave obi_spi_slave_i (
+      .spi_sclk(spi_slave_sck_i),
+      .spi_cs(spi_slave_cs_i),
+      .spi_miso(spi_slave_miso_o),
+      .spi_mosi(spi_slave_mosi_i),
+      .obi_aclk(clk_i),
+      .obi_aresetn(rst_ni),
+      .obi_master_req(spi_slave_req_o.req),
+      .obi_master_gnt(spi_slave_resp_i.gnt),
+      .obi_master_addr(spi_slave_req_o.addr),
+      .obi_master_we(spi_slave_req_o.we),
+      .obi_master_w_data(spi_slave_req_o.wdata),
+      .obi_master_be(spi_slave_req_o.be),
+      .obi_master_r_valid(spi_slave_resp_i.rvalid),
+      .obi_master_r_data(spi_slave_resp_i.rdata)
+  );
+
+
+
+  assign spi_slave_sck_o = 1'b0;
+  assign spi_slave_sck_oe_o = 1'b0;
+  assign spi_slave_cs_o = 1'b0;
+  assign spi_slave_cs_oe_o = 1'b0;
+  assign spi_slave_miso_oe_o = 1'b1;
+  assign spi_slave_mosi_o = 1'b0;
+  assign spi_slave_mosi_oe_o = 1'b0;
+
+
 endmodule : ao_peripheral_subsystem

hw/core-v-mini-mcu/core_v_mini_mcu.sv

@@ -102,22 +102,6 @@ module core_v_mini_mcu
     input  logic gpio_13_i,
     output logic gpio_13_oe_o,
 
-    output logic gpio_14_o,
-    input  logic gpio_14_i,
-    output logic gpio_14_oe_o,
-
-    output logic gpio_15_o,
-    input  logic gpio_15_i,
-    output logic gpio_15_oe_o,
-
-    output logic gpio_16_o,
-    input  logic gpio_16_i,
-    output logic gpio_16_oe_o,
-
-    output logic gpio_17_o,
-    input  logic gpio_17_i,
-    output logic gpio_17_oe_o,
-
     output logic spi_flash_sck_o,
     input  logic spi_flash_sck_i,
     output logic spi_flash_sck_oe_o,
@@ -174,6 +158,34 @@ module core_v_mini_mcu
     input  logic spi_sd_3_i,
     output logic spi_sd_3_oe_o,
 
+    output logic spi_slave_sck_o,
+    input  logic spi_slave_sck_i,
+    output logic spi_slave_sck_oe_o,
+    output logic gpio_14_o,
+    input  logic gpio_14_i,
+    output logic gpio_14_oe_o,
+
+    output logic spi_slave_cs_o,
+    input  logic spi_slave_cs_i,
+    output logic spi_slave_cs_oe_o,
+    output logic gpio_15_o,
+    input  logic gpio_15_i,
+    output logic gpio_15_oe_o,
+
+    output logic spi_slave_miso_o,
+    input  logic spi_slave_miso_i,
+    output logic spi_slave_miso_oe_o,
+    output logic gpio_16_o,
+    input  logic gpio_16_i,
+    output logic gpio_16_oe_o,
+
+    output logic spi_slave_mosi_o,
+    input  logic spi_slave_mosi_i,
+    output logic spi_slave_mosi_oe_o,
+    output logic gpio_17_o,
+    input  logic gpio_17_i,
+    output logic gpio_17_oe_o,
+
     output logic pdm2pcm_pdm_o,
     input  logic pdm2pcm_pdm_i,
     output logic pdm2pcm_pdm_oe_o,
@@ -383,6 +395,10 @@ module core_v_mini_mcu
   obi_req_t peripheral_slave_req;
   obi_resp_t peripheral_slave_resp;
 
+  //OBI SPI slave
+  obi_req_t spi_slave_req;
+  obi_resp_t spi_slave_resp;
+
   // signals to debug unit
   logic debug_core_req;
   logic debug_reset_n;
@@ -459,6 +475,90 @@ module core_v_mini_mcu
   assign memory_subsystem_banks_powergate_iso_n[1] = memory_subsystem_pwr_ctrl_out[1].isogate_en_n;
   assign memory_subsystem_banks_set_retentive_n[1] = memory_subsystem_pwr_ctrl_out[1].retentive_en_n;
   assign memory_subsystem_clkgate_en_n[1] = memory_subsystem_pwr_ctrl_out[1].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[2] = memory_subsystem_pwr_ctrl_out[2].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[2].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[2];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[2] = memory_subsystem_pwr_ctrl_out[2].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[2] = memory_subsystem_pwr_ctrl_out[2].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[2] = memory_subsystem_pwr_ctrl_out[2].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[3] = memory_subsystem_pwr_ctrl_out[3].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[3].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[3];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[3] = memory_subsystem_pwr_ctrl_out[3].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[3] = memory_subsystem_pwr_ctrl_out[3].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[3] = memory_subsystem_pwr_ctrl_out[3].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[4] = memory_subsystem_pwr_ctrl_out[4].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[4].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[4];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[4] = memory_subsystem_pwr_ctrl_out[4].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[4] = memory_subsystem_pwr_ctrl_out[4].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[4] = memory_subsystem_pwr_ctrl_out[4].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[5] = memory_subsystem_pwr_ctrl_out[5].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[5].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[5];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[5] = memory_subsystem_pwr_ctrl_out[5].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[5] = memory_subsystem_pwr_ctrl_out[5].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[5] = memory_subsystem_pwr_ctrl_out[5].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[6] = memory_subsystem_pwr_ctrl_out[6].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[6].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[6];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[6] = memory_subsystem_pwr_ctrl_out[6].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[6] = memory_subsystem_pwr_ctrl_out[6].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[6] = memory_subsystem_pwr_ctrl_out[6].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[7] = memory_subsystem_pwr_ctrl_out[7].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[7].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[7];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[7] = memory_subsystem_pwr_ctrl_out[7].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[7] = memory_subsystem_pwr_ctrl_out[7].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[7] = memory_subsystem_pwr_ctrl_out[7].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[8] = memory_subsystem_pwr_ctrl_out[8].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[8].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[8];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[8] = memory_subsystem_pwr_ctrl_out[8].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[8] = memory_subsystem_pwr_ctrl_out[8].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[8] = memory_subsystem_pwr_ctrl_out[8].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[9] = memory_subsystem_pwr_ctrl_out[9].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[9].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[9];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[9] = memory_subsystem_pwr_ctrl_out[9].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[9] = memory_subsystem_pwr_ctrl_out[9].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[9] = memory_subsystem_pwr_ctrl_out[9].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[10] = memory_subsystem_pwr_ctrl_out[10].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[10].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[10];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[10] = memory_subsystem_pwr_ctrl_out[10].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[10] = memory_subsystem_pwr_ctrl_out[10].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[10] = memory_subsystem_pwr_ctrl_out[10].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[11] = memory_subsystem_pwr_ctrl_out[11].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[11].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[11];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[11] = memory_subsystem_pwr_ctrl_out[11].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[11] = memory_subsystem_pwr_ctrl_out[11].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[11] = memory_subsystem_pwr_ctrl_out[11].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[12] = memory_subsystem_pwr_ctrl_out[12].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[12].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[12];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[12] = memory_subsystem_pwr_ctrl_out[12].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[12] = memory_subsystem_pwr_ctrl_out[12].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[12] = memory_subsystem_pwr_ctrl_out[12].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[13] = memory_subsystem_pwr_ctrl_out[13].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[13].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[13];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[13] = memory_subsystem_pwr_ctrl_out[13].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[13] = memory_subsystem_pwr_ctrl_out[13].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[13] = memory_subsystem_pwr_ctrl_out[13].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[14] = memory_subsystem_pwr_ctrl_out[14].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[14].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[14];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[14] = memory_subsystem_pwr_ctrl_out[14].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[14] = memory_subsystem_pwr_ctrl_out[14].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[14] = memory_subsystem_pwr_ctrl_out[14].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[15] = memory_subsystem_pwr_ctrl_out[15].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[15].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[15];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[15] = memory_subsystem_pwr_ctrl_out[15].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[15] = memory_subsystem_pwr_ctrl_out[15].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[15] = memory_subsystem_pwr_ctrl_out[15].clkgate_en_n;
 
   for (genvar i = 0; i < EXT_DOMAINS_RND; i = i + 1) begin
     assign external_subsystem_powergate_switch_no[i]        = external_subsystem_pwr_ctrl_out[i].pwrgate_en_n;
@@ -604,7 +704,9 @@ module core_v_mini_mcu
       .ext_dma_write_req_o(ext_dma_write_req_o),
       .ext_dma_write_resp_i(ext_dma_write_resp_i),
       .ext_dma_addr_req_o(ext_dma_addr_req_o),
-      .ext_dma_addr_resp_i(ext_dma_addr_resp_i)
+      .ext_dma_addr_resp_i(ext_dma_addr_resp_i),
+      .spi_slave_req_i(spi_slave_req),
+      .spi_slave_resp_o(spi_slave_resp)
   );
 
   memory_subsystem #(
@@ -692,7 +794,21 @@ module core_v_mini_mcu
       .ext_dma_slot_tx_i,
       .ext_dma_slot_rx_i,
       .ext_dma_stop_i,
-      .dma_done_o
+      .dma_done_o,
+      .spi_slave_sck_o(spi_slave_sck_o),
+      .spi_slave_sck_i(spi_slave_sck_i),
+      .spi_slave_sck_oe_o(spi_slave_sck_oe_o),
+      .spi_slave_cs_o(spi_slave_cs_o),
+      .spi_slave_cs_i(spi_slave_cs_i),
+      .spi_slave_cs_oe_o(spi_slave_cs_oe_o),
+      .spi_slave_miso_o(spi_slave_miso_o),
+      .spi_slave_miso_i(spi_slave_miso_i),
+      .spi_slave_miso_oe_o(spi_slave_miso_oe_o),
+      .spi_slave_mosi_o(spi_slave_mosi_o),
+      .spi_slave_mosi_i(spi_slave_mosi_i),
+      .spi_slave_mosi_oe_o(spi_slave_mosi_oe_o),
+      .spi_slave_req_o(spi_slave_req),
+      .spi_slave_resp_i(spi_slave_resp)
   );
 
   peripheral_subsystem peripheral_subsystem_i (

hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl

@@ -137,6 +137,10 @@ ${pad.core_v_mini_mcu_interface}
   obi_req_t peripheral_slave_req;
   obi_resp_t peripheral_slave_resp;
 
+  //OBI SPI slave
+  obi_req_t spi_slave_req;
+  obi_resp_t spi_slave_resp;
+
   // signals to debug unit
   logic debug_core_req;
   logic debug_reset_n;
@@ -354,7 +358,9 @@ ${pad.core_v_mini_mcu_interface}
       .ext_dma_write_req_o(ext_dma_write_req_o),
       .ext_dma_write_resp_i(ext_dma_write_resp_i),
       .ext_dma_addr_req_o(ext_dma_addr_req_o),
-      .ext_dma_addr_resp_i(ext_dma_addr_resp_i)
+      .ext_dma_addr_resp_i(ext_dma_addr_resp_i),
+      .spi_slave_req_i(spi_slave_req),
+      .spi_slave_resp_o(spi_slave_resp)
   );
 
   memory_subsystem #(
@@ -440,7 +446,21 @@ ${pad.core_v_mini_mcu_interface}
       .ext_dma_slot_tx_i,
       .ext_dma_slot_rx_i,
       .ext_dma_stop_i,
-      .dma_done_o
+      .dma_done_o,
+      .spi_slave_sck_o(spi_slave_sck_o),
+      .spi_slave_sck_i(spi_slave_sck_i),
+      .spi_slave_sck_oe_o(spi_slave_sck_oe_o),
+      .spi_slave_cs_o(spi_slave_cs_o),
+      .spi_slave_cs_i(spi_slave_cs_i),
+      .spi_slave_cs_oe_o(spi_slave_cs_oe_o),
+      .spi_slave_miso_o(spi_slave_miso_o),
+      .spi_slave_miso_i(spi_slave_miso_i),
+      .spi_slave_miso_oe_o(spi_slave_miso_oe_o),
+      .spi_slave_mosi_o(spi_slave_mosi_o),
+      .spi_slave_mosi_i(spi_slave_mosi_i),
+      .spi_slave_mosi_oe_o(spi_slave_mosi_oe_o),
+      .spi_slave_req_o(spi_slave_req),
+      .spi_slave_resp_i(spi_slave_resp)
   );
 
   peripheral_subsystem peripheral_subsystem_i (

hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl

@@ -38,11 +38,14 @@ package core_v_mini_mcu_pkg;
   localparam logic [31:0] CORE_INSTR_IDX = 0;
   localparam logic [31:0] CORE_DATA_IDX = 1;
   localparam logic [31:0] DEBUG_MASTER_IDX = 2;
-  localparam logic [31:0] DMA_READ_P0_IDX = 3;
-  localparam logic [31:0] DMA_WRITE_P0_IDX = 4;
-  localparam logic [31:0] DMA_ADDR_P0_IDX = 5;
+  localparam logic [31:0] SPI_SLAVE_IDX = 3;
+  localparam logic [31:0] DMA_READ_P0_IDX = 4;
+  localparam logic [31:0] DMA_WRITE_P0_IDX = 5;
+  localparam logic [31:0] DMA_ADDR_P0_IDX = 6;
+
 
-  localparam SYSTEM_XBAR_NMASTER = ${3 + int(num_dma_master_ports)*3};
+
+  localparam SYSTEM_XBAR_NMASTER = ${4 + int(num_dma_master_ports)*3};
 
   // Internal slave memory map and index
   // -----------------------------------

hw/core-v-mini-mcu/peripheral_subsystem.sv

@@ -70,6 +70,7 @@ module peripheral_subsystem
     output logic [                        3:0] spi2_sd_en_o,
     input  logic [                        3:0] spi2_sd_i,
 
+
     //RV TIMER
     output logic rv_timer_2_intr_o,
     output logic rv_timer_3_intr_o,
@@ -443,8 +444,17 @@ module peripheral_subsystem
       .intr_spi_event_o(spi2_intr_event)
   );
 
-  assign peripheral_slv_rsp[core_v_mini_mcu_pkg::PDM2PCM_IDX] = '0;
-  assign pdm2pcm_clk_o = '0;
+  pdm2pcm #(
+      .reg_req_t(reg_pkg::reg_req_t),
+      .reg_rsp_t(reg_pkg::reg_rsp_t)
+  ) pdm2pcm_i (
+      .clk_i(clk_cg),
+      .rst_ni,
+      .reg_req_i(peripheral_slv_req[core_v_mini_mcu_pkg::PDM2PCM_IDX]),
+      .reg_rsp_o(peripheral_slv_rsp[core_v_mini_mcu_pkg::PDM2PCM_IDX]),
+      .pdm_i(pdm2pcm_pdm_i),
+      .pdm_clk_o(pdm2pcm_clk_o)
+  );
 
   assign pdm2pcm_clk_en_o = 1;
 
@@ -470,4 +480,6 @@ module peripheral_subsystem
       .i2s_rx_valid_o(i2s_rx_valid_o)
   );
 
+
+
 endmodule : peripheral_subsystem

hw/core-v-mini-mcu/peripheral_subsystem.sv.tpl

@@ -70,6 +70,7 @@ module peripheral_subsystem
     output logic [                        3:0] spi2_sd_en_o,
     input  logic [                        3:0] spi2_sd_i,
 
+
     //RV TIMER
     output logic rv_timer_2_intr_o,
     output logic rv_timer_3_intr_o,
@@ -601,4 +602,6 @@ module peripheral_subsystem
 % endif
 % endfor
 
+
+
 endmodule : peripheral_subsystem