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simd: riscv: implement RVV intrinsics #9731
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Signed-off-by: Hiroshi Hatake <[email protected]>
Signed-off-by: Hiroshi Hatake <[email protected]>
Signed-off-by: Hiroshi Hatake <[email protected]>
Signed-off-by: Hiroshi Hatake <[email protected]>
Signed-off-by: Hiroshi Hatake <[email protected]>
Signed-off-by: Hiroshi Hatake <[email protected]>
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Signed-off-by: Hiroshi Hatake <[email protected]>
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In RISC-V intrinsics, RVV (RISC-V "Vector") extensions are existing.
In this PR, I experimented to implement RVV extensions and got succeeded to pass internal and runtime tests with turning on this RVV extensions.
This PR uses RVV v0.11 intrinsics.
Some of the RVV extensions are not corresponding one-by-one to NEON or SSE2.
Plus,
vuint8m1_t
andvuint32m1_t
types do not have fixed size.So, I assumed the fixed lengths for them is 16 like as the result of
sizeof(__m128i)
orsizeof(uint8x16_t)
.Enter
[N/A]
in the box, if an item is not applicable to your change.Testing
Before we can approve your change; please submit the following in a comment:
If this is a change to packaging of containers or native binaries then please confirm it works for all targets.
ok-package-test
label to test for all targets (requires maintainer to do).Documentation
Backporting
Fluent Bit is licensed under Apache 2.0, by submitting this pull request I understand that this code will be released under the terms of that license.