Code

[WIP] Implement a VHDL backend#122

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rlee287 wants to merge 100 commits intoghdl:masterghdl/ghdl-yosys-plugin:masterfrom rlee287:vhdl_backendrlee287/ghdl-yosys-plugin:vhdl_backendCopy head branch name to clipboard

+2,499-4

Commits

Commits on May 21, 2020

• Copy the verilog backend as vhdl_backend.cc

  Show description for e8f73b6
  rlee287

  committed
  e8f73b6

• Replace the copyright header with one styled after the ghdl.cc header

  rlee287

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  0bca471

Commits on May 22, 2020

• Initial labelling of functions as needing porting or not, subject to change

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  6bedabe

• Update Makefiles to build the new backend as well

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  7346b71

• Write VHDL header imports and adjust the autogenerated header comment

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  ac43d36

• Remove useless '\n' terminator argument from dump_attributes

  rlee287

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  7b08be4

Commits on May 23, 2020

• Use log_experimental to log the fact that the VHDL backend is experimental

  rlee287

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  1c8e4cc

• Mark dump_attributes as PORTING REQUIRED again

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  rlee287

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  004a03e

• Implement dump_constant and remove decimal option

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  rlee287

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  698fa75

• Merge branch 'master' into vhdl_backend

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  a4e4c1c

• Port range identifiers in dump_sigchunk

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  14b618c

Commits on May 24, 2020

• Port vector concatenation in dump_sigspec

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  cac7e92

• Remove #if 0 section of dump_wire

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  a6c0fdd

• Port dump_memory function

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  3fe06c7

• Port dump_conn

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  4f56439

Commits on May 25, 2020

• Replace keyword list in id with VHDL keywords

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  d128c86

• Port dump_cell_expr_uniop and dump_cell_expr_binop

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  rlee287

  committed
  6e1b43d

• Replace $signed with signed in dump_cell_expr_port

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  rlee287

  committed
  826226b

Commits on May 28, 2020

• Merge branch 'master' into vhdl_backend

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  29c63ab

Commits on May 30, 2020

• Port syntax gen of is_reg_wire

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  rlee287

  committed
  9e1f859

Commits on May 31, 2020

• Port dump_reg_init

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  committed
  ee90888

Commits on Jun 3, 2020

• Label dump_reg_init as needing testing

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  5b7c9e6

• Port range syntax of dump_wire (port dump still need adjusting)

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  dad6896

• Initial pass of porting dump_cell_expr

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  rlee287

  committed
  ee5c01c

• Wrap uniop and binop operators in casts when doing arithmetic operation

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  b3e271f

Commits on Jun 5, 2020

• Adjustments to autogenerated IDs to ensure numbered internal signals are valid VHDL identifiers

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  38472f6

• Avoid wrapping constants with signed/unsigned conversion functions

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  7103321

• Set default autoprefix of 'n' and enforce nonempty prefix

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  81989ce

• Update dump_cell_expr_(uni/bin)op for dump_cell_expr_port changes

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  6e8b878

• Adjust dump_const to use single quote STD_LOGIC for 1-wide constants

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  a14cf54

• Add warning about 1-length vectors to help string

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  9f79c7d

• Initial port of module dumping

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  rlee287

  committed
  402c7f9

• Port bit selection of cellname

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  rlee287

  committed
  46626fd

Commits on Jun 6, 2020

• Write function to get a sensitivity set given SigSpecs

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  rlee287

  committed
  014f000

• Address Xiretza's review comment

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  rlee287

  committed
  9c31e5b

• Copy over $divfloor and $modfloor updates from Yosys

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• Merge branch 'master' into vhdl_backend

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  474302b

Commits on Jun 8, 2020

• Add get_sensitivity_list signature using initializer_list

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  af3a5b7

• Remove extraneous space before operator in dump_cell_expr_uniop

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  c31fc4a

• Adjust warnings about signals being 1 wide

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  78cc811

• First pass at porting $pmux

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  rlee287

  committed
  83c2768

• Fix $pmux dump to use onehot strings instead of aggregates

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  rlee287

  committed
  8529d14

• Escape ivar_ id's that are incoming as well

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  d7c10fc

Commits on Jun 9, 2020

• Properly port $eq and related

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  rlee287

  committed
  3865d76

Commits on Jun 13, 2020

• Fix capitalization of X and Z states in constants

  rlee287

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  a5e59d0

• For hex consts, push '0's and include width when needed

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  rlee287

  committed
  9cff95b

• Adjustments to some UNIOPs

  rlee287

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  ad5bbc7

• Remove std::set argument version of get_setnsitivity_set

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  6920990

• Print error if dump_wire is called on a port

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  e30fb17

• Remove outdated TODOs and adjust comments

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  ff18f66

• Split the reg-finding part of dump_process into different function

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  9a76111

Commits on Jul 28, 2020

• Replace YS_OVERRIDE macros with override keyword

  rlee287

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  e2259fb

Commits on Aug 2, 2020

• Part 1 of porting new FF changes

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  rlee287

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  6118676

• Misc comments and tidying up

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  157e8b3

Commits on Aug 5, 2020

• Make memory_array_types a regular (sorted) set

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  rlee287

  committed
  6738129

Commits on Aug 7, 2020

• Ignore dump_wire on port instead of raising error

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• Minor adjustments to PSL cell generation

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  f2575f2

Commits on Aug 9, 2020

• Dump $assert cells as regular VHDL assert

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  rlee287

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  6e90b3d

• Apply unary or to $logic_not when required

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  890084e

Commits on Aug 10, 2020

• Write get_sensitivity_set that takes std::set

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  3f9cd3a

• Copy over new dumping code and port clocked FF portions of it

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  rlee287

  committed
  0d23d58

Commits on Aug 11, 2020

• When dumping a PSL cover statement, use a Sequence (Braced-SERE)

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Commits on Aug 14, 2020

• Port latch generation code as well

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  rlee287

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  a319f1a

• Remove obsolete commented-out code for dumping FFs

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  ef2aea4

Commits on Sep 7, 2020

• Merge branch 'master' into vhdl_backend

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  793e1ab

Commits on Sep 26, 2020

• Remove defparam option

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  rlee287

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  f6a24ef

• Copy a change from the Verilog backend

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  f844b44

Commits on Oct 9, 2020

• Create std08 command line option

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• VHDL-93 compliant hex constants when -std08 not specified

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• More updates on dumping FFs

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  1cd293d

• More UNIOP handling

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  rlee287

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  e014176

Commits on Oct 13, 2020

• Remove spacing between chunk name and chunk range

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  95e3d1d

• Replace "unclocked assertions" warning with "unclocked directives"

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  rlee287

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  3b039c3

Commits on Nov 2, 2020

• Rename dump_memory to dump_memory_types

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  rlee287

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  506cc97

Commits on Dec 16, 2020

• Merge branch 'master' into vhdl_backend

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  2f9d312

• Include GHDL plugin version in generated VHDL output

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Commits on Dec 17, 2020

• Improve handling of $assert and friends

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  626a4c0

• Update various comments in VHDL backend code

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  cac3f48

• Adjust emitting of ?= and write explanatory comments

  rlee287

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  613f282

• Port over Mem helper changes from Verilog backend

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  rlee287

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  14e9562

• Port simple_lhs change from Verilog backend

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  ea00e7b

Commits on Dec 20, 2020

• Replace -simple-lhs with -nosimple-lhs and only allow this in VHDL-2008 mode

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  c25d2ab

• Put parentheses around output of dump_cell_expr_port in case concatenation happens

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  rlee287

  committed
  b7967d4

• Fix lingering assignment = in post-synth cell expr dumping

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  fcc110f

• Propagate LHS concatenation mode to various cell_expr dumps

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  rlee287

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  4070425

• Fix mult18x18d component to match yosys verilog

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  JulianKemmerer

  authored and

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  94fec4e

Commits on Dec 21, 2020

• Fix a series of bugs in FF dumping code

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  d7a9032

• Write a process_sensitivity_str helper and use it for process sensitivity lists

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  ff3be34

Commits on Jan 1, 2021

• Merge branch 'master' into vhdl_backend

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  e13584c

Commits on Jan 25, 2021

• Merge branch 'master' into vhdl_backend

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  6111230

Commits on Feb 11, 2021

• Slight adjustments to formal cell dumping

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  rlee287

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  0c6ea58

• Mark dump_memory_types as porting complete

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  rlee287

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  f1b5e3c

• Initial (believed working) port of $lut cell dumping

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  rlee287

  committed
  ad14b39

Commits on Feb 12, 2021

• Log warning when emitting VHDL-2008 LHS aggregates

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  52d1a02

• Fix more FF bugs by rewriting synchronous signal portion

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  38763f2

• Avoid requiring VERSION macro and print "unknown version" if macro is undefined

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  e6b31e2

Commits on Mar 3, 2021

• Update some comments, including an archive source for a (now dead) link

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Commits on Mar 13, 2021

• Merge branch 'master' into vhdl_backend

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  e60aa70

Commits on Mar 18, 2021

• Merge branch 'master' into vhdl_backend

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  1bd4855

Commits on Mar 29, 2021

• Merge branch 'master' into vhdl_backend

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