Adding dualgate table rules

.github/workflows/regression.yml

@@ -29,10 +29,11 @@ jobs:
   regression:
     runs-on: ubuntu-latest
     strategy:
+      max-parallel: 4
       fail-fast: false
       matrix:
         include:
-          - { tool: klayout, part: drc, test: main }
+          - { tool: klayout, part: drc, test: dualgate }
           - { tool: klayout, part: drc, test: switch }
           - { tool: klayout, part: lvs, test: main }
           - { tool: klayout, part: lvs, test: switch }

.gitignore

@@ -3,6 +3,8 @@ __pycache__/
 *.py[cod]
 *$py.class
 
+klayout/drc/testing/unit_tests_*
+
 # C extensions
 *.so
 

Makefile

@@ -22,6 +22,9 @@ REQUIREMENTS_FILE := requirements.txt
 # https://docs.conda.io/projects/conda/en/latest/user-guide/tasks/manage-environments.html
 ENVIRONMENT_FILE := pdk_regression.yml
 
+# Path to regression
+KLAYOUT_TESTS := klayout/drc/testing/
+
 include third_party/make-env/conda.mk
 
 # Lint python code
@@ -31,21 +34,32 @@ lint: | $(CONDA_ENV_PYTHON)
 ################################################################################
 ## DRC Regression section
 ################################################################################
-# DRC main testing
-test-DRC-main: | $(CONDA_ENV_PYTHON)
-	@$(IN_CONDA_ENV) klayout -v
+#=================================
+# ----- test-DRC_regression ------
+#=================================
+.ONESHELL:
+test-DRC-main : | $(CONDA_ENV_PYTHON) 
+	@$(IN_CONDA_ENV) python3 $(KLAYOUT_TESTS)/run_regression.py
 
-# DRC main testing
+.ONESHELL:
+test-DRC-% : | $(CONDA_ENV_PYTHON)
+	@which python3
+	@$(IN_CONDA_ENV) python3 $(KLAYOUT_TESTS)/run_regression.py --table=$*
+
+#=================================
+# -------- test-DRC-switch -------
+#=================================
+# LVS main testing
 test-DRC-switch: | $(CONDA_ENV_PYTHON)
 	@$(IN_CONDA_ENV) klayout -v
 
 ################################################################################
-## DRC Regression section
+## LVS Regression section
 ################################################################################
-# DRC main testing
+# LVS main testing
 test-LVS-main: | $(CONDA_ENV_PYTHON)
 	@$(IN_CONDA_ENV) klayout -v
 
-# DRC main testing
+# LVS main testing
 test-LVS-switch: | $(CONDA_ENV_PYTHON)
 	@$(IN_CONDA_ENV) klayout -v

klayout/drc/README.md

@@ -0,0 +1,82 @@
+# DRC Documentation
+
+Explains how to use the runset.
+
+## Folder Structure
+
+```text
+📁drc
+ ┣ 📁testing
+ ┣ 📁rule_decks
+ ┣ 📜README.md
+ ┗ 📜run_drc.py
+ ```
+
+## Rule Deck Usage
+The `run_drc.py` script takes a gds file to run DRC rule decks of GF180 technology with switches to select subsets of all checks. 
+
+### Requirements
+Please make sure to use the latest Klayout setup at your side. To install klayout, please refer to documentation at [klayout build](https://www.klayout.de/build.html).
+
+Also, please make sure to install the required python packages at `requirements.txt` by using
+```bash
+pip install -r requirements.txt
+```
+
+### Metal Stack Options
+We have a list of metal stack options which corresponds to the following:
+- **Option A** : combined options of metal_level=3, mim_option=A, metal_top=30K, poly_res=1K, and mim_cap=2
+- **Option B** : combined options of metal_level=4, mim_option=B, metal_top=11K, poly_res=1K, and mim_cap=2
+- **Option C** : combined options of metal_level=5, mim_option=B, metal_top=9K,  poly_res=1K, and mim_cap=2
+
+### Usage
+
+```bash
+    run_drc.py (--help| -h)
+    run_drc.py (--path=<file_path>) (--gf180mcu=<combined_options>) [--topcell=<topcell_name>] [--thr=<thr>] [--run_mode=<run_mode>] [--no_feol] [--no_beol] [--connectivity] [--density] [--density_only] [--antenna] [--antenna_only] [--no_offgrid]
+```
+
+Example:
+
+```bash
+    python3 run_drc.py --path=testing/switch_checking/simple_por.gds.gz --thr=16 --run_mode=flat --gf180mcu=A --antenna --no_offgrid
+```
+
+### Options
+
+- `--help -h`                           Print this help message.
+
+- `--path=<file_path>`                  The input GDS file path.
+
+- `--gf180mcu=<combined_options>`       Select combined options of metal_top, mim_option, and metal_level. Allowed values (A, B, C).
+  - gf180mcu=A: Select  metal_top=30K  mim_option=A  metal_level=3LM
+  - gf180mcu=B: Select  metal_top=11K  mim_option=B  metal_level=4LM
+  - gf180mcu=C: Select  metal_top=9K   mim_option=B  metal_level=5LM
+
+- `--topcell=<topcell_name>`            Topcell name to use.
+
+- `--thr=<thr>`                         The number of threads used in run.
+
+- `--run_mode=<run_mode>`               Select klayout mode Allowed modes (flat , deep, tiling). [default: flat]
+
+- `--no_feol`                           Turn off FEOL rules from running.
+
+- `--no_beol`                           Turn off BEOL rules from running.
+
+- `--connectivity`                      Turn on connectivity rules.
+
+- `--density`                           Turn on Density rules.
+
+- `--density_only`                      Turn on Density rules only.
+
+- `--antenna`                           Turn on Antenna checks.
+
+- `--antenna_only`                      Turn on Antenna checks only.
+
+- `--no_offgrid`                        Turn off OFFGRID checking rules.
+
+### **DRC Outputs**
+
+Results will appear at the end of the run logs.
+
+The result is a database file (`<your_design_name>.lyrdb`) of all violations in the same directoy of your design. you could view it on your file using klayout.

klayout/drc/rule_decks/dualgate.drc

@@ -0,0 +1,87 @@
+################################################################################################
+# Copyright 2022 GlobalFoundries PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################################
+
+if FEOL
+    #================================================
+    #--------------------DUALGATE--------------------
+    #================================================
+
+    # Rule DV.1: Min. Dualgate enclose DNWELL. is 0.5µm
+    logger.info("Executing rule DV.1")
+    dv1_l1 = dualgate.enclosing(dnwell, 0.5.um, euclidian).polygons(0.001)
+    dv1_l2 = dnwell.not_outside(dualgate).not(dualgate)
+    dv1_l  = dv1_l1.or(dv1_l2)
+    dv1_l.output("DV.1", "DV.1 : Min. Dualgate enclose DNWELL. : 0.5µm")
+    dv1_l1.forget
+    dv1_l2.forget
+    dv1_l.forget
+
+    # Rule DV.2: Min. Dualgate Space. Merge if Space is less than this design rule. is 0.44µm
+    logger.info("Executing rule DV.2")
+    dv2_l1  = dualgate.space(0.44.um, euclidian).polygons(0.001)
+    dv2_l1.output("DV.2", "DV.2 : Min. Dualgate Space. Merge if Space is less than this design rule. : 0.44µm")
+    dv2_l1.forget
+
+    # Rule DV.3: Min. Dualgate to COMP space [unrelated]. is 0.24µm
+    logger.info("Executing rule DV.3")
+    dv3_l1  = dualgate.separation(comp.outside(dualgate), 0.24.um, euclidian).polygons(0.001)
+    dv3_l1.output("DV.3", "DV.3 : Min. Dualgate to COMP space [unrelated]. : 0.24µm")
+    dv3_l1.forget
+
+    # rule DV.4 is not a DRC check
+
+    # Rule DV.5: Min. Dualgate width. is 0.7µm
+    logger.info("Executing rule DV.5")
+    dv5_l1  = dualgate.width(0.7.um, euclidian).polygons(0.001)
+    dv5_l1.output("DV.5", "DV.5 : Min. Dualgate width. : 0.7µm")
+    dv5_l1.forget
+
+    comp_dv = comp.not(pcomp.outside(nwell))
+    # Rule DV.6: Min. Dualgate enclose COMP (except substrate tap). is 0.24µm
+    logger.info("Executing rule DV.6")
+    dv6_l1 = dualgate.enclosing(comp_dv, 0.24.um, euclidian).polygons(0.001)
+    dv6_l2 = comp_dv.not_outside(dualgate).not(dualgate)
+    dv6_l  = dv6_l1.or(dv6_l2)
+    dv6_l.output("DV.6", "DV.6 : Min. Dualgate enclose COMP (except substrate tap). : 0.24µm")
+    dv6_l1.forget
+    dv6_l2.forget
+    dv6_l.forget
+
+    # Rule DV.7: COMP (except substrate tap) can not be partially overlapped by Dualgate.
+    logger.info("Executing rule DV.7")
+    dv7_l1 = dualgate.not_outside(comp_dv).not(dualgate.covering(comp_dv))
+    dv7_l1.output("DV.7", "DV.7 : COMP (except substrate tap) can not be partially overlapped by Dualgate.")
+    dv7_l1.forget
+
+    comp_dv.forget
+
+    # Rule DV.8: Min Dualgate enclose Poly2. is 0.4µm
+    logger.info("Executing rule DV.8")
+    dv8_l1 = dualgate.enclosing(poly2, 0.4.um, euclidian).polygons(0.001)
+    dv8_l2 = poly2.not_outside(dualgate).not(dualgate)
+    dv8_l  = dv8_l1.or(dv8_l2)
+    dv8_l.output("DV.8", "DV.8 : Min Dualgate enclose Poly2. : 0.4µm")
+    dv8_l1.forget
+    dv8_l2.forget
+    dv8_l.forget
+
+    # Rule DV.9: 3.3V and 5V/6V PMOS cannot be sitting inside same NWELL.
+    logger.info("Executing rule DV.9")
+    dv9_l1 = nwell.covering(pgate.and(dualgate)).covering(pgate.not_inside(v5_xtor).not_inside(dualgate))
+    dv9_l1.output("DV.9", "DV.9 : 3.3V and 5V/6V PMOS cannot be sitting inside same NWELL.")
+    dv9_l1.forget
+end #FEOL
+