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sim/icarus: use multiline block syntax for the summary string (#178)
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umarcor authored Apr 24, 2022
2 parents 287a1db + 07d973d commit 8f32f78
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3 changes: 0 additions & 3 deletions sim/icarus/build.sh
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,3 @@ sh ./autoconf.sh

make -j$CPU_COUNT
make install

$PREFIX/bin/iverilog -V
$PREFIX/bin/iverilog -h || true
7 changes: 6 additions & 1 deletion sim/icarus/meta.yaml
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Expand Up @@ -57,4 +57,9 @@ about:
home: http://iverilog.icarus.com/
license: GPLv2
license_file: COPYING
summary: 'Icarus Verilog (iverilog) is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlists in the desired format.'
summary: |
Icarus Verilog (iverilog) is a Verilog simulation and synthesis tool.
It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format.
For batch simulation, the compiler can generate an intermediate form called vvp assembly.
This intermediate form is executed by the ``vvp'' command.
For synthesis, the compiler generates netlists in the desired format.'

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