Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

riscv64: replace deprecated legacy extensions to SBI 2.0 extensions #1088

Merged
merged 1 commit into from
Apr 17, 2024
Merged

riscv64: replace deprecated legacy extensions to SBI 2.0 extensions #1088

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
17 changes: 13 additions & 4 deletions Cargo.lock
View file
Open in desktop

Some generated files are not rendered by default. Learn more about how customized files appear on GitHub.

2 changes: 1 addition & 1 deletion Cargo.toml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -137,7 +137,7 @@ semihosting = { version = "0.1", optional = true }

[target.'cfg(target_arch = "riscv64")'.dependencies]
riscv = "0.11"
sbi = "0.2"
sbi-rt = "0.0.3"
trapframe = "0.9"
semihosting = { version = "0.1", optional = true }

Expand Down
4 changes: 2 additions & 2 deletions src/arch/riscv64/kernel/mod.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -123,7 +123,7 @@ pub fn message_output_init() {

pub fn output_message_buf(buf: &[u8]) {
for byte in buf {
sbi::legacy::console_putchar(*byte);
sbi_rt::console_write_byte(*byte);
}
}

Expand Down Expand Up @@ -198,7 +198,7 @@ fn finish_processor_init() {

//When running bare-metal/QEMU we use the firmware to start the next hart
if !env::is_uhyve() {
sbi::hart_state_management::hart_start(
sbi_rt::hart_start(
next_hart_id as usize,
start::_start as usize,
RAW_BOOT_INFO.load(Ordering::Relaxed) as usize,
Expand Down
11 changes: 7 additions & 4 deletions src/arch/riscv64/kernel/processor.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -234,7 +234,10 @@ pub fn shutdown(error_code: i32) -> ! {
semihosting::process::exit(error_code)
} else {
// use SBI shutdown
sbi::legacy::shutdown()
sbi_rt::system_reset(sbi_rt::Shutdown, sbi_rt::NoReason);
loop {
core::hint::spin_loop();
}
}
}
}
Expand Down Expand Up @@ -270,16 +273,16 @@ pub fn set_oneshot_timer(wakeup_time: Option<u64>) {
}
let next_time = wt * u64::from(get_frequency());

sbi::legacy::set_timer(next_time);
sbi_rt::set_timer(next_time);
} else {
// Disable the Timer (and clear a pending interrupt)
debug!("Stopping Timer");
sbi::legacy::set_timer(u64::MAX);
sbi_rt::set_timer(u64::MAX);
}
}

pub fn wakeup_core(core_to_wakeup: CoreId) {
let hart_id = unsafe { HARTS_AVAILABLE[core_to_wakeup as usize] };
debug!("Wakeup core: {} , hart_id: {}", core_to_wakeup, hart_id);
sbi::legacy::send_ipi(&[1 << hart_id]);
sbi_rt::send_ipi(sbi_rt::HartMask::from_mask_base(0b1, hart_id));
}