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[GSoC] Common Verilog Generation API and Implementation in temp-sense-gen #212

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merged 32 commits into from
Jul 18, 2023
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832f830
feat: added mako to Python requirements.txt
harshkhandeparkar May 27, 2023
45d2c60
feat: exported a verilog generation function
harshkhandeparkar May 28, 2023
7c58dbd
doc: added code hints to verilog generation functions
harshkhandeparkar May 28, 2023
60d11e9
feat: use the new verilog generation function in temp-sense-gen.
harshkhandeparkar May 29, 2023
5b4363e
feat: converted temp-sense-gen Verilog to Mako templates
harshkhandeparkar May 29, 2023
d305499
fix: fixed typos in TEMP_ANALOG_lv.v
harshkhandeparkar May 29, 2023
98fb956
fix: changed placeholder port nbout to X
harshkhandeparkar May 29, 2023
688859b
feat: updated gitignore files
harshkhandeparkar May 29, 2023
5e18789
fix: removed unused imports in temp-sense-gen.py
harshkhandeparkar May 29, 2023
ac85fb9
fix: removed extra tabs in Verilog source
harshkhandeparkar May 29, 2023
1a3bbd6
fix: removed a statement which incremented ninv
harshkhandeparkar May 29, 2023
ef5a28f
feat: commented unused code
harshkhandeparkar May 29, 2023
9524faf
feat: added designName as a parameter in the Verilog source
harshkhandeparkar May 29, 2023
3d74ba4
feat: designName parameter code
harshkhandeparkar May 29, 2023
835b9b6
feat: removed previous code
harshkhandeparkar May 29, 2023
441f004
feat: removed `.template` replacement
harshkhandeparkar May 29, 2023
a55f30f
refactor: rename counter_generic.v to counter.v
harshkhandeparkar May 29, 2023
eef004f
feat: clean the generated verilog files in make clean
harshkhandeparkar May 29, 2023
70c120e
docs: added docstrings to common API
harshkhandeparkar May 30, 2023
115747f
feat: pre-imported common defs
harshkhandeparkar May 30, 2023
67660e9
feat: removed old commented Verilog code
harshkhandeparkar May 31, 2023
c8e8518
fix: fixed generation of `blocks/sky130hd/*.txt`
harshkhandeparkar Jun 3, 2023
6d38d10
refactor: convert all class privates to module privates
harshkhandeparkar Jun 5, 2023
677bf9f
test: added unit tests for the _generate_file function
harshkhandeparkar Jun 5, 2023
d97616b
test: added better error message in asserts
harshkhandeparkar Jun 5, 2023
2e5dda3
test: added tests for files in subdirectory
harshkhandeparkar Jun 7, 2023
cc0f3b5
docs: update flow-tempsense.rst to reflect the changes
harshkhandeparkar Jun 7, 2023
a0e4ee4
feat: export a map of common platform prefixes in verilog_generation …
harshkhandeparkar Jun 9, 2023
07eab48
feat: used the exported prefix map in temp sensor
harshkhandeparkar Jun 9, 2023
32f6336
docs: added docstrings for the prefix map
harshkhandeparkar Jun 9, 2023
d8cd281
docs: added common python module docs to sphinx documentation
harshkhandeparkar Jun 21, 2023
cbf4381
docs: mention the Common Python API in tempsense docs
harshkhandeparkar Jun 21, 2023
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feat: use the new verilog generation function in temp-sense-gen.
  • Loading branch information
harshkhandeparkar committed May 29, 2023
commit 60d11e902e0de3a3f23b65eefdd59e24e80c8276
103 changes: 61 additions & 42 deletions openfasoc/generators/temp-sense-gen/tools/temp-sense-gen.py
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,10 @@
from readparamgen import args, check_search_done, designName
from simulation import generate_runs

sys.path.append(os.path.join(os.path.dirname(__file__), '..', '..'))

from common.verilog_generation import generate_verilog

genDir = os.path.join(os.path.dirname(os.path.relpath(__file__)), "../")
srcDir = genDir + "src/"
flowDir = genDir + "flow/"
Expand Down Expand Up @@ -115,50 +119,65 @@
aux6 = "SLC_hs"

ninv = ninv + 1
TEMP_netlist.gen_temp_netlist(ninv, nhead, aux1, aux2, aux3, aux4, aux5, srcDir)

with open(srcDir + "TEMP_ANALOG_hv.nl.v", "r") as rf:
filedata = rf.read()
header_list = re.findall("HEADER\s+(\w+)\(", filedata)
with open(genDir + "blocks/sky130hd/tempsenseInst_custom_net.txt", "w") as wf:
wf.write("r_VIN\n")
for header_cell in header_list:
wf.write("temp_analog_1." + header_cell + " VIN\n")

with open(srcDir + "TEMP_ANALOG_lv.nl.v", "r") as rf:
filedata = rf.read()
lv_list = re.findall("\nsky130_fd_sc\w*\s+(\w+)\s+\(", filedata)
with open(genDir + "blocks/sky130hd/tempsenseInst_domain_insts.txt", "w") as wf:
for lv_cell in lv_list:
wf.write("temp_analog_0." + lv_cell + "\n")

with open(srcDir + "tempsenseInst.v", "r") as rf:
filedata = rf.read()
filedata = re.sub("module\s*(\w+)\s*\n", "module " + designName + "\n", filedata)
with open(srcDir + "tempsenseInst.v", "w") as wf:
wf.write(filedata)

with open(flowDir + "design/sky130hd/tempsense/config.mk", "r") as rf:
filedata = rf.read()
filedata = re.sub(
"export DESIGN_NAME\s*=\s*(\w+)", "export DESIGN_NAME = " + designName, filedata
)
with open(flowDir + "design/sky130hd/tempsense/config.mk", "w") as wf:
wf.write(filedata)

shutil.copyfile(
srcDir + "TEMP_ANALOG_lv.nl.v", flowDir + "design/src/tempsense/TEMP_ANALOG_lv.nl.v"
)
shutil.copyfile(
srcDir + "TEMP_ANALOG_hv.nl.v", flowDir + "design/src/tempsense/TEMP_ANALOG_hv.nl.v"
# TODO: Previous code. Remove later.
# TEMP_netlist.gen_temp_netlist(ninv, nhead, aux1, aux2, aux3, aux4, aux5, srcDir)

generate_verilog(
parameters={
"cell_prefix": "sky130_fd_sc_hd__" if args.platform == "sky130hd" else "sky130_fd_sc_hs__",
"cell_suffix": "_1",
"header_cell": "HEADER" if args.platform == "sky130hd" else "HEADER_hs",
"slc_cell": "SLC" if args.platform == "sky130hd" else "SLC_hs",
"ninv": ninv,
"nhead": nhead
},
out_dir=os.path.join('flow', 'design', 'src', 'tempsense')
)
shutil.copyfile(
srcDir + "TEMP_AUTO_def.v", flowDir + "design/src/tempsense/TEMP_AUTO_def.v"
)
shutil.copyfile(
srcDir + "tempsenseInst.v", flowDir + "design/src/tempsense/" + designName + ".v"
)
shutil.copyfile(srcDir + "counter.v", flowDir + "design/src/tempsense/counter" + ".v")

# TODO: Previous code. Remove later.
# with open(srcDir + "TEMP_ANALOG_hv.nl.v", "r") as rf:
# filedata = rf.read()
# header_list = re.findall("HEADER\s+(\w+)\(", filedata)
# with open(genDir + "blocks/sky130hd/tempsenseInst_custom_net.txt", "w") as wf:
# wf.write("r_VIN\n")
# for header_cell in header_list:
# wf.write("temp_analog_1." + header_cell + " VIN\n")

# with open(srcDir + "TEMP_ANALOG_lv.nl.v", "r") as rf:
# filedata = rf.read()
# lv_list = re.findall("\nsky130_fd_sc\w*\s+(\w+)\s+\(", filedata)
# with open(genDir + "blocks/sky130hd/tempsenseInst_domain_insts.txt", "w") as wf:
# for lv_cell in lv_list:
# wf.write("temp_analog_0." + lv_cell + "\n")

# with open(srcDir + "tempsenseInst.v", "r") as rf:
# filedata = rf.read()
# filedata = re.sub("module\s*(\w+)\s*\n", "module " + designName + "\n", filedata)
# with open(srcDir + "tempsenseInst.v", "w") as wf:
# wf.write(filedata)

# with open(flowDir + "design/sky130hd/tempsense/config.mk", "r") as rf:
# filedata = rf.read()
# filedata = re.sub(
# "export DESIGN_NAME\s*=\s*(\w+)", "export DESIGN_NAME = " + designName, filedata
# )
# with open(flowDir + "design/sky130hd/tempsense/config.mk", "w") as wf:
# wf.write(filedata)

# shutil.copyfile(
# srcDir + "TEMP_ANALOG_lv.nl.v", flowDir + "design/src/tempsense/TEMP_ANALOG_lv.nl.v"
# )
# shutil.copyfile(
# srcDir + "TEMP_ANALOG_hv.nl.v", flowDir + "design/src/tempsense/TEMP_ANALOG_hv.nl.v"
# )
# shutil.copyfile(
# srcDir + "TEMP_AUTO_def.v", flowDir + "design/src/tempsense/TEMP_AUTO_def.v"
# )
# shutil.copyfile(
# srcDir + "tempsenseInst.v", flowDir + "design/src/tempsense/" + designName + ".v"
# )
# shutil.copyfile(srcDir + "counter.v", flowDir + "design/src/tempsense/counter" + ".v")

print("#----------------------------------------------------------------------")
print("# Verilog Generated")
Expand Down