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[GSoC] Common Verilog Generation API and Implementation in temp-sense-gen #212

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merged 32 commits into from
Jul 18, 2023
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832f830
feat: added mako to Python requirements.txt
harshkhandeparkar May 27, 2023
45d2c60
feat: exported a verilog generation function
harshkhandeparkar May 28, 2023
7c58dbd
doc: added code hints to verilog generation functions
harshkhandeparkar May 28, 2023
60d11e9
feat: use the new verilog generation function in temp-sense-gen.
harshkhandeparkar May 29, 2023
5b4363e
feat: converted temp-sense-gen Verilog to Mako templates
harshkhandeparkar May 29, 2023
d305499
fix: fixed typos in TEMP_ANALOG_lv.v
harshkhandeparkar May 29, 2023
98fb956
fix: changed placeholder port nbout to X
harshkhandeparkar May 29, 2023
688859b
feat: updated gitignore files
harshkhandeparkar May 29, 2023
5e18789
fix: removed unused imports in temp-sense-gen.py
harshkhandeparkar May 29, 2023
ac85fb9
fix: removed extra tabs in Verilog source
harshkhandeparkar May 29, 2023
1a3bbd6
fix: removed a statement which incremented ninv
harshkhandeparkar May 29, 2023
ef5a28f
feat: commented unused code
harshkhandeparkar May 29, 2023
9524faf
feat: added designName as a parameter in the Verilog source
harshkhandeparkar May 29, 2023
3d74ba4
feat: designName parameter code
harshkhandeparkar May 29, 2023
835b9b6
feat: removed previous code
harshkhandeparkar May 29, 2023
441f004
feat: removed `.template` replacement
harshkhandeparkar May 29, 2023
a55f30f
refactor: rename counter_generic.v to counter.v
harshkhandeparkar May 29, 2023
eef004f
feat: clean the generated verilog files in make clean
harshkhandeparkar May 29, 2023
70c120e
docs: added docstrings to common API
harshkhandeparkar May 30, 2023
115747f
feat: pre-imported common defs
harshkhandeparkar May 30, 2023
67660e9
feat: removed old commented Verilog code
harshkhandeparkar May 31, 2023
c8e8518
fix: fixed generation of `blocks/sky130hd/*.txt`
harshkhandeparkar Jun 3, 2023
6d38d10
refactor: convert all class privates to module privates
harshkhandeparkar Jun 5, 2023
677bf9f
test: added unit tests for the _generate_file function
harshkhandeparkar Jun 5, 2023
d97616b
test: added better error message in asserts
harshkhandeparkar Jun 5, 2023
2e5dda3
test: added tests for files in subdirectory
harshkhandeparkar Jun 7, 2023
cc0f3b5
docs: update flow-tempsense.rst to reflect the changes
harshkhandeparkar Jun 7, 2023
a0e4ee4
feat: export a map of common platform prefixes in verilog_generation …
harshkhandeparkar Jun 9, 2023
07eab48
feat: used the exported prefix map in temp sensor
harshkhandeparkar Jun 9, 2023
32f6336
docs: added docstrings for the prefix map
harshkhandeparkar Jun 9, 2023
d8cd281
docs: added common python module docs to sphinx documentation
harshkhandeparkar Jun 21, 2023
cbf4381
docs: mention the Common Python API in tempsense docs
harshkhandeparkar Jun 21, 2023
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docs: update flow-tempsense.rst to reflect the changes
* updated any filenames and links that have changed
* mentioned the use of Mako syntax
  • Loading branch information
harshkhandeparkar committed Jun 7, 2023
commit cc0f3b571d2083eeb7316e3d15fa25767d60cd77
25 changes: 13 additions & 12 deletions docs/source/flow-tempsense.rst
Original file line number Diff line number Diff line change
Expand Up @@ -45,20 +45,21 @@ Verilog generation
Running ``make sky130hd_temp`` (temp for "temperature sensor") executes the `temp-sense-gen.py <https://github.com/idea-fasoc/OpenFASOC/blob/main/openfasoc/generators/temp-sense-gen/tools/temp-sense-gen.py>`_ script from temp-sense-gen/tools/. This file takes the input specifications from `test.json <https://github.com/idea-fasoc/OpenFASOC/blob/main/openfasoc/generators/temp-sense-gen/test.json>`_ and outputs Verilog files containing the description of the circuit.

.. note::
temp-sense-gen.py calls other modules from temp-sense-gen/tools/ during execution. For example, `readparamgen.py <https://github.com/idea-fasoc/OpenFASOC/blob/main/openfasoc/generators/temp-sense-gen/tools/readparamgen.py>`_ is in charge of reading test.json, checking for correct user input and choosing the correct circuit elements.
temp-sense-gen.py calls other modules from temp-sense-gen/tools/ and generators/common/ during execution. For example, `readparamgen.py <https://github.com/idea-fasoc/OpenFASOC/blob/main/openfasoc/generators/temp-sense-gen/tools/readparamgen.py>`_ is in charge of reading test.json, checking for correct user input and choosing the correct circuit elements.

The generator starts from a Verilog template of the temperature sensor circuit, located in `temp-sense-gen/src/ <https://github.com/idea-fasoc/OpenFASOC/tree/main/openfasoc/generators/temp-sense-gen/src>`_. The ``.v`` template files have lines marked with ``@@``, which are replaced according to the specifications.
The generator starts from a Verilog template of the temperature sensor circuit, located in `temp-sense-gen/src/ <https://github.com/idea-fasoc/OpenFASOC/tree/main/openfasoc/generators/temp-sense-gen/src>`_. The ``.v`` templates follow `Mako <https://makotemplates.org>`_ syntax. For example, ``${param}`` is replaced with the value of the parameter ``param``.

Example: `counter_generic.v line 31 <https://github.com/idea-fasoc/OpenFASOC/blob/main/openfasoc/generators/temp-sense-gen/src/counter_generic.v#L31>`_ is replaced during Verilog generation.
Example: In `counter.v line 31 <https://github.com/idea-fasoc/OpenFASOC/blob/main/openfasoc/generators/temp-sense-gen/src/counter.v#L32>`_, ``${cell('buf')}`` with the buffer cell which is ``sky130_fd_sc_hd__buf_1`` for sky130hd.

.. code-block:: verilog
:emphasize-lines: 3
:emphasize-lines: 4
:linenos:
:lineno-start: 29

assign done_sens = WAKE_pre && doneb;
assign done_ref = WAKE && doneb;
@@ @np Buf_DONE(.A(done_pre), .nbout(DONE));
assign done_ref = WAKE && doneb;

${cell('buf')} Buf_DONE(.A(done_pre), .X(DONE));

always @ (*) begin
case (done_pre)
Expand Down Expand Up @@ -87,15 +88,15 @@ OpenROAD Flow takes a design from the temp-sense-gen/flow/design/ directory and
└── design
├── sky130hd
│ └── tempsense
│ ├── config.mk <--
│ ├── config.mk <--
│ └── constraint.sdc
└── src
└── tempsense
├── counter.v <--
├── TEMP_ANALOG_hv.nl.v <--
├── TEMP_ANALOG_lv.nl.v <--
├── TEMP_AUTO_def.v <--
└── tempsenseInst_error.v <--
├── counter.v <--
├── TEMP_ANALOG_hv.v <--
├── TEMP_ANALOG_lv.v <--
├── TEMP_AUTO_def.v <--
└── tempsenseInst.v <--

For more information on OpenROAD Flow, check their `docs <https://openroad.readthedocs.io/en/latest/user/GettingStarted.html>`_.

Expand Down