Chipathon2024 Mahowald-ers Cascode Common Source Block #339
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…ove the M2 north of M1.
…horizontal or vertical placement.
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@chetanyagoyal / @srpathen , 
`Circuit 1 contains 6 devices, Circuit 2 contains 2 devices. *** MISMATCH *** Final result: Logging to file "/tmp/tmp4n_a1thr/cascode_common_source_lvs_lvs.rpt" disabled Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes. Subcircuit pins:
Cell pin lists are equivalent. Class cascode_common_source_lvs (0): Merged 8 parallel devices.
NET mismatches: Class fragments follow (with fanout counts): Net: w_n780_n522# |Net: IOUT
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| Circuit 1: cascode_common_source_lvs | Circuit 2: cascode_common_source_lvs |
|---|---|
| (no matching pin) | VIN |
| (no matching pin) | VBIAS |
| (no matching pin) | VSS |
| (no matching pin) | IOUT |
| proxyIOUT | (no matching pin) |
Cell pin lists for cascode_common_source_lvs and cascode_common_source_lvs altered to match.
Device classes cascode_common_source_lvs and cascode_common_source_lvs are equivalent.
Final result: Top level cell failed pin matching.
`
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I've added the rectangular Pins and labels using add_label() and align_comp_to_port(). As a result the label and rectangular ports are visible on metal 1 as shown below. However, LVS is still failing as the export component doesn't recognize the ports as components. 
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Subcircuit pins:
Cell pin lists for cascode_common_source_lvs and cascode_common_source_lvs altered to match. Final result: Top level cell failed pin matching. ` |
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@chetanyagoyal could you kindly clarify the netlist function used for the LVS check as the lvs fail implies that the Netlist is not getting extracted with the correct pins. ` return Netlist( ` Also the extract scipt gave the following error whenused with the gds ` Magic 8.3 revision 464 - Compiled on Sat Mar 9 23:18:29 UTC 2024. |
Apologies for the late replies, you can just dump the netlist from the python function to a file ( Try modifying the function until the dumped netlist matches your expectations |
Sud-ana
changed the title
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LVS checks are in progress. Have added the ports to the layout . LVS checks are still failing. Subcircuit pins:
Cell pin lists are equivalent. Subcircuit summary:
NET mismatches: Class fragments follow (with fanout counts): Net: IOUT |Net: IOUT
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| Circuit 1: cascode_common_source_lvs | Circuit 2: cascode_common_source_lvs |
|---|---|
| (no pins) | VBIAS Mismatch |
| (no matching pin) | VIN |
| (no matching pin) | VSS |
| (no matching pin) | IOUT |
| (no matching pin) | INT |
Cell pin lists for cascode_common_source_lvs and cascode_common_source_lvs altered to match.
Device classes cascode_common_source_lvs and cascode_common_source_lvs are equivalent.
Final result: Top level cell failed pin matching.`
Unable to store the LVS, DRC results in DRC, LVS directory as I see error below
magic_drc_result = sky130.drc_magic(Cascode_cs_component, Cascode_cs_component.name, output_file_path="DRC/") File "/usr/bin/miniconda3/lib/python3.10/site-packages/pydantic/deprecated/decorator.py", line 55, in wrapper_function return vd.call(*args, **kwargs) File "/usr/bin/miniconda3/lib/python3.10/site-packages/pydantic/deprecated/decorator.py", line 149, in call m = self.init_model_instance(*args, **kwargs) File "/usr/bin/miniconda3/lib/python3.10/site-packages/pydantic/deprecated/decorator.py", line 146, in init_model_instance return self.model(**values) File "/usr/bin/miniconda3/lib/python3.10/site-packages/pydantic/main.py", line 209, in __init__ validated_self = self.__pydantic_validator__.validate_python(data, self_instance=self) File "/usr/bin/miniconda3/lib/python3.10/site-packages/pydantic/deprecated/decorator.py", line 255, in check_kwargs raise TypeError(f'unexpected keyword argument{plural}: {keys}') TypeError: unexpected keyword argument: 'output_file_path'
…LVS but netlist fails to match. Debug required.
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The LVS passes when all the bulks are tied to VSS for NMOS, but I cannot short the M2 bulk to M2 source. The LVS fails when each bulk is connected to it's source ports. Please feedback on how to short the bulk to the source. `Logging to file "/tmp/tmp79w4dkic/cascode_common_source_lvs_lvs.rpt" disabled Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes. Subcircuit pins:
Cell pin lists are equivalent. Subcircuit summary:
Netlists match uniquely. Subcircuit pins:
Cell pin lists are equivalent. Final result: Circuits match uniquely.
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| instance_format = "X{name} {nodes} {circuit_name} l={length} w={width} m={mult}" | ||
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| return Netlist( |
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You do not need to construct the whole netlist. You can use the sub-devices (the NMOS) and use python to construct the netlist.
| with_dummy=False, #with_dummy, | ||
| with_substrate_tap=False, | ||
| **kwargs) | ||
| print("FETS are instantiated now") |
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Is this required? It might clutter the logs. Perhaps it can be changed to give out slightly more specific information.
| if device in ['nmos', 'nfet']: | ||
| print(f"NMOS device") | ||
| # add a pwell | ||
| top_level.add_padding(layers = (pdk.get_glayer("pwell"),), default = pdk.get_grule("pwell", "active_tap")["min_enclosure"], ) |
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Both of these statements only change the value nwell or pwell, code duplication can be reduced.
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| generated_netlist_for_lvs = top_level.info['netlist'].generate_netlist() | ||
| print(f"Type of generated netlist is :", generated_netlist_for_lvs) |
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It would be good if this is done outside the function. This function returns a component, the extra code may cause unintended side effects.
| print(f"Verify the file availability and type: ", generated_netlist_for_lvs, type(generated_netlist_for_lvs)) | ||
| return top_level | ||
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| # Function to add labels to the port definitions |
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This can be moved into a docstring.
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| return CMS.flatten() | ||
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| mapped_pdk_build = sky130 |
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This code should also be in a separate file.
| top_level = Component("cascode common source amplifier") | ||
| # Create the transistors | ||
| print(f"Creating ", device, " devices with these parameters: ",m1_fingers,m1_multipliers, m2_fingers, m2_multipliers) | ||
| if device in ['nmos', 'nfet']: |
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Code duplication can be reduced in the FET instantiation as only the type of fet changes with the rest of the code being same.
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Thanks harshkhandeparkar for the feedbacks. Will work on them and address the comments. Thanks. |
PR for a cascode common source . LVS is failing with
Final result: Top level cell failed pin matching. Please review and let us know the function parameters for LVS.