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Chipathon2024 Mahowald-ers Cascode Common Source Block #339

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Chipathon2024 Mahowald-ers Cascode Common Source Block #339

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15687d1
Added the cascode common source amplifier with interdigitated fingers.
Sud-ana Sep 12, 2024
c3fe9f8
Added the M1 and M2 FETs to top_level component. Reference added to m…
Sud-ana Sep 12, 2024
2d20695
Added reference to the input and cascode transistor with options for …
Sud-ana Sep 19, 2024
92efd11
Source of M2 connected to Drain of M1 with generic port definition.
Sud-ana Sep 19, 2024
f1909b3
Added port prefix M1 and M2 .
Sud-ana Sep 19, 2024
d0b1504
Removed comments
Sud-ana Sep 19, 2024
fb86c0a
LVS fails.
Sud-ana Sep 19, 2024
ce42551
LVS fail again.
Sud-ana Sep 19, 2024
7340dcc
Multiple fingers and multipliers supported for the NMOS/PMOS devices.
Sud-ana Sep 23, 2024
d3e2f02
Documentation function updted
Sud-ana Sep 23, 2024
f0ad2de
comment updated
Sud-ana Sep 23, 2024
fe2ae5e
Adding ports
Sud-ana Oct 2, 2024
32e2fcd
Adding ports
Sud-ana Oct 3, 2024
c0bbccd
Adding ports
Sud-ana Oct 4, 2024
e8bb0b4
Updated the netlist function.
Sud-ana Oct 9, 2024
460b303
Port size reduced.
Sud-ana Oct 9, 2024
4fb49f9
Port labelling added.
Sud-ana Nov 10, 2024
ef9615b
Removed the XDUMMY transistor devices
Sud-ana Nov 16, 2024
242bd03
Alternative pin placement for VIN VBIAS IIN VSS.
Sud-ana Nov 28, 2024
bbf4ea5
Adding the labels for the ports.
Sud-ana Nov 28, 2024
139840e
Added the layer labels for the nets and pins.
Sud-ana Nov 28, 2024
1994d1b
GLayout has 6 nets while schematic has 5nets. Pin list matches after …
Sud-ana Nov 28, 2024
2188092
LVS matches for layout and schematic.
Sud-ana Nov 29, 2024
1fdd82d
Cleaning up the code.
Sud-ana Dec 11, 2024
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1 change: 1 addition & 0 deletions ...fasoc/generators/glayout/glayout/flow/blocks/elementary/cascode_common_source/__init__.py
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from glayout.flow.blocks.elementary.cascode_common_source.cascode_common_source import cascode_common_source, cascode_common_source_netlist
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