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Merge pull request hdl#253 from antmicro/52551-adder_mapping_pass
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Synthesis: Add fa/ha extract and techmap pass
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@mithro
mithro authored Dec 21, 2023
2 parents ad55931 + 67f5b43 commit 63cc3d4
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1 change: 1 addition & 0 deletions dependency_support/com_google_skywater_pdk/sky130_fd_sc_hd/BUILD
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Expand Up @@ -49,4 +49,5 @@ open_road_pdk_configuration(
],
wire_rc_clock_metal_layer = "met5",
wire_rc_signal_metal_layer = "met2",
ha_fa_mapping = "cell_adders.v"
)
49 changes: 49 additions & 0 deletions dependency_support/com_google_skywater_pdk/sky130_fd_sc_hd/cell_adders.v
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@@ -0,0 +1,49 @@
// File copy form OpenRAOD-flow-scripts@dd552435616bcc18fb2dba0b221f682d9e873fb1
// Works only with sky130_fd_sc_hd
(* techmap_celltype = "$fa" *)
module _tech_fa (A, B, C, X, Y);
parameter WIDTH = 1;
(* force_downto *)
input [WIDTH-1 : 0] A, B, C;
(* force_downto *)
output [WIDTH-1 : 0] X, Y;

parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx;
parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx;
parameter _TECHMAP_CONSTVAL_C_ = WIDTH'bx;

genvar i;
generate for (i = 0; i < WIDTH; i = i + 1) begin
if (_TECHMAP_CONSTVAL_A_[i] === 1'b0 || _TECHMAP_CONSTVAL_B_[i] === 1'b0 || _TECHMAP_CONSTVAL_C_[i] === 1'b0) begin
if (_TECHMAP_CONSTVAL_C_[i] === 1'b0) begin
sky130_fd_sc_hd__ha_1 halfadder_Cconst (
.A(A[i]),
.B(B[i]),
.COUT(X[i]), .SUM(Y[i])
);
end
else begin
if (_TECHMAP_CONSTVAL_B_[i] === 1'b0) begin
sky130_fd_sc_hd__ha_1 halfadder_Bconst (
.A(A[i]),
.B(C[i]),
.COUT(X[i]), .SUM(Y[i])
);
end
else begin
sky130_fd_sc_hd__ha_1 halfadder_Aconst (
.A(B[i]),
.B(C[i]),
.COUT(X[i]), .SUM(Y[i])
);
end
end
end
else begin
sky130_fd_sc_hd__fa_1 fulladder (
.A(A[i]), .B(B[i]), .CIN(C[i]), .COUT(X[i]), .SUM(Y[i])
);
end
end endgenerate

endmodule
3 changes: 3 additions & 0 deletions dependency_support/org_theopenroadproject_asap7_pdk_r1p7/BUILD
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Expand Up @@ -25,4 +25,7 @@ exports_files([
"pdn_config_1x.pdn", # FIXME: Where did this come from?
"pdn_config_4x.pdn", # FIXME: Where did this come from?
"asap7.lyt", # Imported from OpenROAD-flow-scripts on 24.07.2023 at 6ec980e1d49a1a8dcdd1e25ed81255b4bb8285c8 from: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/6ec980e1d49a1a8dcdd1e25ed81255b4bb8285c8/flow/platforms/asap7/KLayout/asap7.lyt
"cell_adders_R.v",
"cell_adders_L.v",
"cell_adders_SL.v",
])
56 changes: 56 additions & 0 deletions dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cell_adders_L.v
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// File copy form
// OpenRAOD-flow-scripts@dd552435616bcc18fb2dba0b221f682d9e873fb1
// Only works with asap7 L cell library
(* techmap_celltype = "$fa" *)
module _tech_fa (A, B, C, X, Y);
parameter WIDTH = 1;
(* force_downto *)
input [WIDTH-1 : 0] A, B, C;
(* force_downto *)
output [WIDTH-1 : 0] X, Y;

wire [WIDTH-1 : 0] NX, NY;

parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx;
parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx;
parameter _TECHMAP_CONSTVAL_C_ = WIDTH'bx;

genvar i;
generate for (i = 0; i < WIDTH; i = i + 1) begin
if (_TECHMAP_CONSTVAL_A_[i] === 1'b0 || _TECHMAP_CONSTVAL_B_[i] === 1'b0 || _TECHMAP_CONSTVAL_C_[i] === 1'b0) begin
if (_TECHMAP_CONSTVAL_C_[i] === 1'b0) begin
HAxp5_ASAP7_75t_L halfadder_Cconst (
.A(A[i]),
.B(B[i]),
.CON(NX[i]), .SN(NY[i])
);
end
else begin
if (_TECHMAP_CONSTVAL_B_[i] === 1'b0) begin
HAxp5_ASAP7_75t_L halfadder_Bconst (
.A(A[i]),
.B(C[i]),
.CON(NX[i]), .SN(NY[i])
);
end
else begin
HAxp5_ASAP7_75t_L halfadder_Aconst (
.A(B[i]),
.B(C[i]),
.CON(NX[i]), .SN(NY[i])
);
end
end
end
else begin
FAx1_ASAP7_75t_L fulladder (
.A(A[i]), .B(B[i]), .CI(C[i]), .CON(NX[i]), .SN(NY[i])
);
end

assign X[i] = ~NX[i];
assign Y[i] = ~NY[i];

end endgenerate

endmodule
56 changes: 56 additions & 0 deletions dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cell_adders_R.v
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// File copy form
// OpenRAOD-flow-scripts@dd552435616bcc18fb2dba0b221f682d9e873fb1
// Only works with asap7 R cell library
(* techmap_celltype = "$fa" *)
module _tech_fa (A, B, C, X, Y);
parameter WIDTH = 1;
(* force_downto *)
input [WIDTH-1 : 0] A, B, C;
(* force_downto *)
output [WIDTH-1 : 0] X, Y;

wire [WIDTH-1 : 0] NX, NY;

parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx;
parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx;
parameter _TECHMAP_CONSTVAL_C_ = WIDTH'bx;

genvar i;
generate for (i = 0; i < WIDTH; i = i + 1) begin
if (_TECHMAP_CONSTVAL_A_[i] === 1'b0 || _TECHMAP_CONSTVAL_B_[i] === 1'b0 || _TECHMAP_CONSTVAL_C_[i] === 1'b0) begin
if (_TECHMAP_CONSTVAL_C_[i] === 1'b0) begin
HAxp5_ASAP7_75t_R halfadder_Cconst (
.A(A[i]),
.B(B[i]),
.CON(NX[i]), .SN(NY[i])
);
end
else begin
if (_TECHMAP_CONSTVAL_B_[i] === 1'b0) begin
HAxp5_ASAP7_75t_R halfadder_Bconst (
.A(A[i]),
.B(C[i]),
.CON(NX[i]), .SN(NY[i])
);
end
else begin
HAxp5_ASAP7_75t_R halfadder_Aconst (
.A(B[i]),
.B(C[i]),
.CON(NX[i]), .SN(NY[i])
);
end
end
end
else begin
FAx1_ASAP7_75t_R fulladder (
.A(A[i]), .B(B[i]), .CI(C[i]), .CON(NX[i]), .SN(NY[i])
);
end

assign X[i] = ~NX[i];
assign Y[i] = ~NY[i];

end endgenerate

endmodule
56 changes: 56 additions & 0 deletions dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cell_adders_SL.v
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// File copy form
// OpenRAOD-flow-scripts@dd552435616bcc18fb2dba0b221f682d9e873fb1
// Only works with asap7 R cell library
(* techmap_celltype = "$fa" *)
module _tech_fa (A, B, C, X, Y);
parameter WIDTH = 1;
(* force_downto *)
input [WIDTH-1 : 0] A, B, C;
(* force_downto *)
output [WIDTH-1 : 0] X, Y;

wire [WIDTH-1 : 0] NX, NY;

parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx;
parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx;
parameter _TECHMAP_CONSTVAL_C_ = WIDTH'bx;

genvar i;
generate for (i = 0; i < WIDTH; i = i + 1) begin
if (_TECHMAP_CONSTVAL_A_[i] === 1'b0 || _TECHMAP_CONSTVAL_B_[i] === 1'b0 || _TECHMAP_CONSTVAL_C_[i] === 1'b0) begin
if (_TECHMAP_CONSTVAL_C_[i] === 1'b0) begin
HAxp5_ASAP7_75t_SL halfadder_Cconst (
.A(A[i]),
.B(B[i]),
.CON(NX[i]), .SN(NY[i])
);
end
else begin
if (_TECHMAP_CONSTVAL_B_[i] === 1'b0) begin
HAxp5_ASAP7_75t_SL halfadder_Bconst (
.A(A[i]),
.B(C[i]),
.CON(NX[i]), .SN(NY[i])
);
end
else begin
HAxp5_ASAP7_75t_SL halfadder_Aconst (
.A(B[i]),
.B(C[i]),
.CON(NX[i]), .SN(NY[i])
);
end
end
end
else begin
FAx1_ASAP7_75t_SL fulladder (
.A(A[i]), .B(B[i]), .CI(C[i]), .CON(NX[i]), .SN(NY[i])
);
end

assign X[i] = ~NX[i];
assign Y[i] = ~NY[i];

end endgenerate

endmodule
4 changes: 4 additions & 0 deletions dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel
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Expand Up @@ -103,6 +103,7 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_L.v",
)

# From org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl
Expand Down Expand Up @@ -162,6 +163,7 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v",
)

# From org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl
Expand Down Expand Up @@ -287,6 +289,7 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_4x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v",
)

##########################################################################
Expand Down Expand Up @@ -349,6 +352,7 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_SL.v",
)

# From org_theopenroadproject_asap7sc7p5t_27/common.bzl
Expand Down
1 change: 1 addition & 0 deletions dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-lvt.bzl
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Expand Up @@ -68,4 +68,5 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_L.v",
)
1 change: 1 addition & 0 deletions dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl
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Expand Up @@ -68,4 +68,5 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v",
)
1 change: 1 addition & 0 deletions dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl
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Expand Up @@ -134,6 +134,7 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_4x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v",
)

##########################################################################
Expand Down
1 change: 1 addition & 0 deletions dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-slvt.bzl
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Expand Up @@ -68,4 +68,5 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_SL.v",
)
3 changes: 3 additions & 0 deletions dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel
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Expand Up @@ -102,6 +102,7 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_L.v",
)

# From org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl
Expand Down Expand Up @@ -160,6 +161,7 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v",
)

# From org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl
Expand Down Expand Up @@ -218,6 +220,7 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_SL.v",
)

# From org_theopenroadproject_asap7sc7p5t_28/common.bzl
Expand Down
1 change: 1 addition & 0 deletions dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-lvt.bzl
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Expand Up @@ -67,4 +67,5 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_L.v",
)
1 change: 1 addition & 0 deletions dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl
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Original file line number Diff line number Diff line change
Expand Up @@ -67,4 +67,5 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v",
)
1 change: 1 addition & 0 deletions dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl
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Original file line number Diff line number Diff line change
Expand Up @@ -67,4 +67,5 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_SL.v",
)
1 change: 1 addition & 0 deletions pdk/build_defs.bzl
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Expand Up @@ -23,6 +23,7 @@ StandardCellInfo = provider(
"tech_lef": "Tech LEF file for the PDK",
"cell_lef_definitions": "list of Abstract LEFs files for each standard cell.",
"platform_gds": "list of Platform GDS files.",
"ha_fa_mapping": "HA/FA techmapping file",
"parasitic_extraction_benchmark": "Optional calibration file for OpenRCX.",
"open_road_configuration": "OpenROAD PDK configuration.",
},
Expand Down
3 changes: 3 additions & 0 deletions pdk/open_road_configuration.bzl
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Expand Up @@ -31,6 +31,7 @@ OpenRoadPdkInfo = provider(
"do_not_use_cell_list": "Do not use cells in timing repair. This supports wild card * cell names",
"cts_buffer_cell": "Clock Tree Buffer cell",
"fill_cells": "Metal fill cells",
"ha_fa_mapping": "HA/FA techmapping file",
"global_routing_layer_adjustments": "Global routing adjustment layers",
"global_routing_clock_layers": "Clock routing layers",
"global_routing_signal_layers": "Signal routing layers",
Expand Down Expand Up @@ -69,6 +70,7 @@ def _open_road_pdk_configuration_impl(ctx):
do_not_use_cell_list = ctx.attr.do_not_use_cell_list,
cts_buffer_cell = ctx.attr.cts_buffer_cell,
fill_cells = ctx.attr.fill_cells,
ha_fa_mapping = ctx.attr.ha_fa_mapping,
global_routing_layer_adjustments = ctx.attr.global_routing_layer_adjustments,
global_routing_clock_layers = ctx.attr.global_routing_clock_layers,
global_routing_signal_layers = ctx.attr.global_routing_signal_layers,
Expand Down Expand Up @@ -102,6 +104,7 @@ open_road_pdk_configuration = rule(
"do_not_use_cell_list": attr.string_list(mandatory = True, doc = "This value can be an empty list if all cells should be used in P&R"),
"cts_buffer_cell": attr.string(mandatory = True, doc = "Clock Tree Buffer cell"),
"fill_cells": attr.string_list(mandatory = True),
"ha_fa_mapping": attr.label(allow_single_file = True, doc = "Yosys specific HA/FA techmapping file"),
"global_routing_layer_adjustments": attr.string_dict(mandatory = True),
"global_routing_clock_layers": attr.string(mandatory = True),
"global_routing_signal_layers": attr.string(mandatory = True),
Expand Down
10 changes: 10 additions & 0 deletions synthesis/build_defs.bzl
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Original file line number Diff line number Diff line change
Expand Up @@ -136,6 +136,12 @@ def _synthesize_design_impl(ctx):
if or_config.tie_high_port:
script_env_files["TIEHI_CELL_AND_PORT"] = str(or_config.tie_high_port)

ha_fa_mapping = or_config.ha_fa_mapping
if ha_fa_mapping:
ha_fa_mapping_path = ha_fa_mapping.files.to_list()[0].path
script_env_files["ADDER_MAPPING"] = str(ha_fa_mapping_path)
inputs.append(ha_fa_mapping.files.to_list()[0])

env = {
"YOSYS_DATDIR": yosys_runfiles_dir + "/at_clifford_yosys/techlibs/",
"ABC": yosys_runfiles_dir + "/edu_berkeley_abc/abc",
Expand Down Expand Up @@ -259,6 +265,10 @@ synthesize_rtl = rule(
allow_single_file = True,
doc = "Tcl synthesis script compatible with the environment-variable API of synth.tcl",
),
"adder_mapping": attr.label(
allow_single_file = True,
doc = "Verilog file that maps yosys adder to PDK adders."
),
"target_clock_period_pico_seconds": attr.int(doc = "target clock period in picoseconds"),
"output_file_name": attr.string(doc = "The output file name."),
},
Expand Down
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