Refactor tests.

 * Test each step by itself.

 * Create a `basic_asic_flow` and use it to test each configured
   standard cell libraries for both supported PDKs (`SKY130` & `ASAP7`).

 * Remove the `asap7.bzl` as the `for_each_XXX_cells` macro and
   `basic_asic_flow` are a better replacement.

 * Rename `counter.v` to `verilog_counter.v` to be consistent with
   `verilog_adder.v`.

Signed-off-by: Tim 'mithro' Ansell <[email protected]>
Signed-off-by: Tim Ansell <[email protected]>

flows/basic_asic.bzl

@@ -0,0 +1,130 @@
+# Copyright 2023 Google LLC
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""Very basic ASIC flow, mainly used for testing and debugging."""
+
+load("@bazel_skylib//rules:build_test.bzl", "build_test")
+load("//gds_write:build_defs.bzl", "gds_write")
+load("//place_and_route:build_defs.bzl", "place_and_route")
+load("//static_timing:build_defs.bzl", "run_opensta")
+load("//synthesis:build_defs.bzl", "synthesize_rtl")
+
+def _get_with_defaults(target_name, extra_args, defaults):
+    target_extra_args = extra_args.pop(target_name, {})
+    for k, v in defaults.items():
+        if k not in target_extra_args:
+            target_extra_args[k] = v
+    return target_extra_args
+
+def basic_asic_flow(name, target, cells, top = None, extra_args = {}, gds = True, size = 20):
+    """Generate targets for a basic ASIC flow.
+
+    Args:
+        name: Name for the macro instance.
+        target: Verilog library name.
+        cells: Standard cells to use.
+        top: Name of the top level module (defaults to name).
+        gds: Run all the way to GDS output.
+        extra_args: Extra arguments to provide the steps in the flow.
+        size: Size of the die in microns.
+    """
+    if top == None:
+        top = name
+    extra_args = dict(**extra_args)
+
+    # Synthesis
+    synthesize_rtl(
+        name = name + "-step1-synth",
+        standard_cells = cells,
+        top_module = top,
+        deps = [
+            target,
+        ],
+        **_get_with_defaults(
+            "synthesize_rtl",
+            extra_args,
+            dict(
+                target_clock_period_pico_seconds = 10000,
+            ),
+        )
+    )
+    build_test(
+        name = "build-" + name + "-step1-synth",
+        targets = [":" + name + "-step1-synth"],
+    )
+
+    # Static timing analysis of synthesis result
+    run_opensta(
+        name = name + "-step1-synth_sta",
+        synth_target = ":" + name + "-step1-synth",
+        **_get_with_defaults(
+            "synth_run_opensta",
+            extra_args,
+            dict(
+                # No defaults at the moment.
+            ),
+        )
+    )
+    build_test(
+        name = "build-" + name + "-step1-synth_sta",
+        targets = [":" + name + "-step1-synth_sta"],
+    )
+
+    # Place and Route
+    place_and_route(
+        name = name + "-step2-place_and_route",
+        synthesized_rtl = ":" + name + "-step1-synth",
+        **_get_with_defaults(
+            "place_and_route",
+            extra_args,
+            dict(
+                placement_density = "0.65",
+                core_padding_microns = 1,
+                die_height_microns = size,
+                die_width_microns = size,
+            ),
+        )
+    )
+    build_test(
+        name = "build-" + name + "-step2-place_and_route",
+        targets = [
+            ":" + name + "-step2-place_and_route",
+        ],
+    )
+
+    # FIXME: Should add a post place and route run_opensta?
+
+    # GDS Generation
+    if gds:
+        gds_write(
+            name = name + "-step3-gds",
+            implemented_rtl = ":" + name + "-step2-place_and_route",
+            **_get_with_defaults(
+                "gds_write",
+                extra_args,
+                dict(
+                    # No defaults at the moment.
+                ),
+            )
+        )
+        build_test(
+            name = "build-" + name + "-step3-gds",
+            targets = [
+                ":" + name + "-step3-gds",
+            ],
+        )
+
+    # Make sure everything in the extra_args dictionary has been used.
+    if extra_args:
+        fail("{} provided in 'extra_args' was not used, please remove.".format("and ".join(extra_args.keys())))

pdk/build_defs.bzl

@@ -12,8 +12,7 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
-"""Providers for PDKs to be used by downstream synthesis.
-"""
+"""Providers for PDKs to be used by downstream synthesis."""
 
 StandardCellInfo = provider(
     "Contains information about the standard cells used for synthesis",
@@ -53,6 +52,12 @@ StandardCellOptionsInfo = provider(
 def temp_format(i):
     """Format an integer representing degrees celsius.
 
+    Args:
+        i: Temperature as integer in degrees celsius.
+
+    Returns:
+        A formated string version of input.
+
     The format is:
         * Always 4 characters long.
         * Always ends in lower case 'c'.
@@ -90,7 +95,13 @@ def temp_format(i):
     return s + "c"
 
 def temp_parse(s):
-    """Parse into an int a string representing temperature in degrees celsius.
+    """Parse a string representing temperature in degrees celsius into integer.
+
+    Args:
+        s: Temperature as string.
+
+    Returns:
+        An integer representing temperature in degrees celsius.
 
     >>> temp_parse("030c")
     30
@@ -116,7 +127,7 @@ def temp_parse(s):
 
     # Check string ends in `c` (for degree celsius)
     if s[-1] != "c":
-        fail("No `c` character found at end of value {}".format(s))
+        fail("No `c` character found at end of value {} (input {})".format(s, os))
     s = s[:-1]
 
     # Convert `m` into negative sign
@@ -137,6 +148,12 @@ def temp_parse(s):
 def temp_normalize(s):
     """Normalize an already existing temperature string into the format provided by `temp_format`.
 
+    Args:
+        s: Temperature as string.
+
+    Returns:
+        A normalize version of the input string.
+
     >>> temp_normalize("m2c")
     "m02c"
 
@@ -154,6 +171,12 @@ def temp_normalize(s):
 def voltage_format(f):
     """Format a decimal number representing a voltage.
 
+    Args:
+        f: Voltage as decimal number (float / int).
+
+    Returns:
+        A string version of the input.
+
     The format is:
         * Always 5 characters long.
         * Has one digit before the decimal point.
@@ -189,6 +212,12 @@ def voltage_format(f):
 def voltage_normalize(s):
     """Normalize an existing voltage string into the format provided by `voltage_format`.
 
+    Args:
+        s: Voltage as string.
+
+    Returns:
+        A normalize version of the input string.
+
     >>> voltage_normalize("7p5v")
     "7v500"
 
@@ -197,13 +226,18 @@ def voltage_normalize(s):
 
     >>> voltage_normalize("7.5v")
     "7v500"
-
     """
     return voltage_format(voltage_parse(s))
 
 def voltage_parse(s):
     """Parse a voltage string like that produced by `voltage_format` function.
 
+    Args:
+        s: Voltage as string.
+
+    Returns:
+        A float version of the input string.
+
     >>> voltage_parse("7p5")
     7.5
 

place_and_route/build_defs.bzl

@@ -105,6 +105,6 @@ place_and_route = rule(
         "sink_clustering_size": attr.int(doc = "Clock tree synthesis sink group size"),
         "sink_clustering_max_diameter": attr.int(doc = "Clock tree synthesis sink group desired diamater in microns"),
         "min_pin_distance": attr.string(doc = "The minimum distance in microns between pins around the outside of the block."),
-        "enable_improve_placement": attr.bool(default=True, doc = "Enable/Disable improve_placement pass.")
+        "enable_improve_placement": attr.bool(default = True, doc = "Enable/Disable improve_placement pass."),
     },
 )

place_and_route/private/detailed_routing.bzl

@@ -57,7 +57,7 @@ def detailed_routing(ctx, open_road_info):
 
     open_road_commands = timing_setup_command_struct.commands + [
         "set_propagated_clock [all_clocks]",
-        "detailed_route -output_drc {} {}".format(output_drc.path, detailed_routing_args)
+        "detailed_route -output_drc {} {}".format(output_drc.path, detailed_routing_args),
     ]
     density_fill_config = None
     if open_road_configuration.density_fill_config: