Adding all ASAP7 standard cell libraries.

Signed-off-by: Tim 'mithro' Ansell <[email protected]>

dependency_support/org_theopenroadproject_asap7/asap7sc6t_rev26.bzl

@@ -0,0 +1,264 @@
+# Copyright 2022 Google LLC
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+""" ASAP7 "rev 26" 6 track standard cell library (with SRAM blocks). """
+
+# Layouts for GDS generation
+# ------------------------------------------------------------------------
+
+# Standard cells
+filegroup(
+    name = "gds_cells_rvt",
+    srcs = ["asap7sc6t_26/GDS/asap7sc6t_26_R.gds"],
+    visibility = [":data_visibility"],
+)
+
+filegroup(
+    name = "gds_cells_lvt",
+    srcs = ["asap7sc6t_26/GDS/asap7sc6t_26_L.gds"],
+    visibility = [":data_visibility"],
+)
+
+filegroup(
+    name = "gds_cells_slvt",
+    srcs = ["asap7sc6t_26/GDS/asap7sc6t_26_SL.gds"],
+    visibility = [":data_visibility"],
+)
+
+# SRAM
+filegroup(
+    name = "gds_sram",
+    srcs = ["asap7sc6t_26/GDS/asap7sc6t_26_SRAM.gds"],
+    visibility = [":data_visibility"],
+)
+
+# Timing information (in compressed Liberty format) for synthesis and static
+# timing analysis (STA).
+# ------------------------------------------------------------------------
+
+# Standard cells
+filegroup(
+    name = "libgz_cells_rvt",
+    srcs = glob(["asap7sc6t_26/LIB/CCS/*RVT*.lib.gz"]),
+    visibility = [":data_visibility"],
+)
+
+filegroup(
+    name = "libgz_cells_lvt",
+    srcs = glob(["asap7sc6t_26/LIB/CCS/*LVT*.lib.gz"]),
+    visibility = [":data_visibility"],
+)
+
+filegroup(
+    name = "libgz_cells_slvt",
+    srcs = glob(["asap7sc6t_26/LIB/CCS/*SLVT*.lib.gz"]),
+    visibility = [":data_visibility"],
+)
+
+# SRAM
+filegroup(
+    name = "libgz_sram",
+    srcs = glob(["asap7sc6t_26/LIB/CCS/*SRAM*.lib.gz"]),
+    visibility = [":data_visibility"],
+)
+
+# FIXME: What about NLDM liberty?
+
+# Verilog models for digital simulation and logical equivalence
+# ------------------------------------------------------------------------
+
+# Standard cells
+filegroup(
+    name = "v_cells_rvt",
+    srcs = [
+        "asap7sc6t_26/Verilog/asap7sc7p5t_CKINVDC_RVT_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_AO_RVT_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_INVBUF_RVT_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_OA_RVT_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_SEQ_RVT_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_SIMPLE_RVT_TT_210930.v",
+    ],
+    visibility = [":data_visibility"],
+)
+
+filegroup(
+    name = "v_cells_lvt",
+    srcs = [
+        "asap7sc6t_26/Verilog/asap7sc7p5t_CKINVDC_LVT_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_AO_LVT_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_INVBUF_LVT_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_OA_LVT_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_SEQ_LVT_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_SIMPLE_LVT_TT_210930.v",
+    ],
+    visibility = [":data_visibility"],
+)
+
+filegroup(
+    name = "v_cells_slvt",
+    srcs = [
+        "asap7sc6t_26/Verilog/asap7sc7p5t_CKINVDC_SLVT_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_AO_SLVT_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_INVBUF_SLVT_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_OA_SLVT_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_SEQ_SLVT_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_SIMPLE_SLVT_TT_210930.v",
+    ],
+    visibility = [":data_visibility"],
+)
+
+# SRAM
+filegroup(
+    name = "v_sram",
+    srcs = [
+        "asap7sc6t_26/Verilog/asap7sc7p5t_CKINVDC_SRAM_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_AO_SRAM_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_INVBUF_SRAM_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_OA_SRAM_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_SEQ_SRAM_TT_210930.v",
+        "asap7sc6t_26/Verilog/asap7sc7p5t_SIMPLE_SRAM_TT_210930.v",
+    ],
+    visibility = [":data_visibility"],
+)
+
+# CDL models for LVS checking
+# ------------------------------------------------------------------------
+
+# Standard cells
+filegroup(
+    name = "lvs_cells_rvt",
+    srcs = ["asap7sc6t_26/CDL/LVS/asap7sc6t_26_R.cdl"],
+    visibility = [":data_visibility"],
+)
+
+filegroup(
+    name = "lvs_cells_lvt",
+    srcs = ["asap7sc6t_26/CDL/LVS/asap7sc6t_26_L.cdl"],
+    visibility = [":data_visibility"],
+)
+
+filegroup(
+    name = "lvs_cells_slvt",
+    srcs = ["asap7sc6t_26/CDL/LVS/asap7sc6t_26_SL.cdl"],
+    visibility = [":data_visibility"],
+)
+
+# SRAM
+filegroup(
+    name = "lvs_sram",
+    srcs = ["asap7sc6t_26/CDL/LVS/asap7sc6t_26_SRAM.cdl"],
+    visibility = [":data_visibility"],
+)
+
+# CDL models for Spice simulation
+# ------------------------------------------------------------------------
+
+# Standard cells
+filegroup(
+    name = "spice_cells_rvt",
+    srcs = ["asap7sc6t_26/CDL/xAct3D_extracted/asap7sc6t_26_L_211010.sp"],
+    visibility = [":data_visibility"],
+)
+
+filegroup(
+    name = "spice_cells_lvt",
+    srcs = ["asap7sc6t_26/CDL/xAct3D_extracted/asap7sc6t_26_R_211010.sp"],
+    visibility = [":data_visibility"],
+)
+
+filegroup(
+    name = "spice_cells_slvt",
+    srcs = ["asap7sc6t_26/CDL/xAct3D_extracted/asap7sc6t_26_SL_211010.sp"],
+    visibility = [":data_visibility"],
+)
+
+# SRAM
+filegroup(
+    name = "spice_sram",
+    srcs = ["asap7sc6t_26/CDL/xAct3D_extracted/asap7sc6t_26_SRAM_211010.sp"],
+    visibility = [":data_visibility"],
+)
+
+# Place and route
+# ------------------------------------------------------------------------
+
+# Standard cells
+filegroup(
+    name = "lef_cells_rvt",
+    srcs = ["asap7sc6t_26/LEF/asap7sc6t_26_R_1x_210923b.lef"],
+    visibility = [":data_visibility"],
+)
+
+filegroup(
+    name = "lef_cells_lvt",
+    srcs = ["asap7sc6t_26/LEF/asap7sc6t_26_L_1x_210923b.lef"],
+    visibility = [":data_visibility"],
+)
+
+filegroup(
+    name = "lef_cells_slvt",
+    srcs = ["asap7sc6t_26/LEF/asap7sc6t_26_SL_1x_210923b.lef"],
+    visibility = [":data_visibility"],
+)
+
+# SRAM
+filegroup(
+    name = "lef_sram",
+    srcs = ["asap7sc6t_26/LEF/asap7sc6t_26_SRAM_1x_210923b.lef"],
+    visibility = [":data_visibility"],
+)
+
+# Misc cells
+# FIXME: Where is the 1x techlef?
+#filegroup(
+#    name = "lef_tech",
+#    srcs = ["asap7sc6t_26/techlef_misc/asap7_tech_1x_201209.lef"],
+#    visibility = [":data_visibility"],
+#)
+
+# Alternative cells scaled up to 4x their original size.
+# --------------------------------------------------------------------
+
+# Standard cells
+filegroup(
+    name = "lef_cells_4x_rvt",
+    srcs = ["asap7sc6t_26/LEF/scaled/asap7sc6t_26_R_4x_210923b.lef"],
+    visibility = [":data_visibility"],
+)
+
+filegroup(
+    name = "lef_cells_4x_lvt",
+    srcs = ["asap7sc6t_26/LEF/scaled/asap7sc6t_26_L_4x_210923b.lef"],
+    visibility = [":data_visibility"],
+)
+
+filegroup(
+    name = "lef_cells_4x_slvt",
+    srcs = ["asap7sc6t_26/LEF/scaled/asap7sc6t_26_SL_4x_210923b.lef"],
+    visibility = [":data_visibility"],
+)
+
+# SRAM
+filegroup(
+    name = "lef_sram_4x",
+    srcs = ["asap7sc6t_26/LEF/scaled/asap7sc6t_26_SRAM_4x_210923b.lef"],
+    visibility = [":data_visibility"],
+)
+
+# Misc cell layouts for place and route
+filegroup(
+    name = "lef_tech_4x",
+    srcs = ["asap7sc6t_26/techlef_misc/asap7_tech_4x_201209.lef"],
+    visibility = [":data_visibility"],
+)