Merge pull request hdl#252 from antmicro/52551-tie_logic_levels

Synthesis: Insert tie cells during synthesis

synthesis/build_defs.bzl

@@ -130,6 +130,12 @@ def _synthesize_design_impl(ctx):
     if ctx.attr.target_clock_period_pico_seconds:
         script_env_files["CLOCK_PERIOD"] = str(ctx.attr.target_clock_period_pico_seconds)
 
+    if or_config.tie_low_port:
+        script_env_files["TIELO_CELL_AND_PORT"] = str(or_config.tie_low_port)
+
+    if or_config.tie_high_port:
+        script_env_files["TIEHI_CELL_AND_PORT"] = str(or_config.tie_high_port)
+
     env = {
         "YOSYS_DATDIR": yosys_runfiles_dir + "/at_clifford_yosys/techlibs/",
         "ABC": yosys_runfiles_dir + "/edu_berkeley_abc/abc",

synthesis/synth.tcl

@@ -82,6 +82,22 @@ if { [info exists ::env(CLOCK_PERIOD) ] } {
   abc -liberty $liberty -dff -g aig {*}$::env(DONT_USE_ARGS)
 }
 
+setundef -zero
+splitnets
+opt_clean -purge
+
+if {[info exists ::env(TIEHI_CELL_AND_PORT)] && [info exists ::env(TIELO_CELL_AND_PORT)]} {
+  hilomap \
+        -hicell {*}[split $::env(TIEHI_CELL_AND_PORT) "/"] \
+        -locell {*}[split $::env(TIELO_CELL_AND_PORT) "/"]
+} elseif { [info exists ::env(TIEHI_CELL_AND_PORT)] } {
+  hilomap \
+        -hicell {*}$::env(TIEHI_CELL_AND_PORT)
+} elseif { [info exists ::env(TIELO_CELL_AND_PORT)] } {
+  hilomap \
+        -locell {*}$::env(TIELO_CELL_AND_PORT)
+}
+
 # Remove internal only aliases for public nets and then give created instances
 # useful names. At this stage it is anything generated by the techmapping
 # passes.
@@ -101,7 +117,7 @@ if { [info exists ::env(STATS_JSON) ] } {
 read_liberty -lib -ignore_miss_func $liberty
 ltp -noff $top
 
-yosys log -n Flop count:\ 
+yosys log -n Flop count:\
 yosys select -count t:*__df* t:DFF* t:*_DFF* t:*_SDFF* t:*_ADFF* t:*dff
 
 set base_liberty [file tail $liberty]