Support I_SERDES CLK_OUT (#1680)

* Support I_SERDES CLK_OUT * cleanup * Incremented patch version * Format * Update test input --------- Co-authored-by: chungshien-chai <[email protected]> Co-authored-by: alaindargelas <[email protected]>
os-fpga · Aug 26, 2024 · f42d454 · f42d454
1 parent eb56f3f
commit f42d454
Show file tree

Hide file tree

Showing 14 changed files with 965 additions and 826 deletions.
diff --git a/src/Configuration/ModelConfig/ModelConfig_IO.cpp b/src/Configuration/ModelConfig/ModelConfig_IO.cpp
diff --git a/src/Configuration/ModelConfig/ModelConfig_IO.h b/src/Configuration/ModelConfig/ModelConfig_IO.h
@@ -107,8 +107,7 @@ class ModelConfig_IO {
                                     const std::string& port);
   void allocate_pll_fclk_routing(nlohmann::json& instance,
                                  const std::string& port);
-  void allocate_root_bank_clkmux();
-  void allocate_root_bank_clkmux(nlohmann::json& instance, bool is_pll);
+  void allocate_and_set_root_bank_routing();
   void set_clkbuf_config_attributes();
   void set_clkbuf_config_attribute(nlohmann::json& instance);
   void allocate_pll();

diff --git a/tests/unittest/ModelConfig/apis/config_attributes.mapping.json b/tests/unittest/ModelConfig/apis/config_attributes.mapping.json
@@ -110,6 +110,25 @@
         "I_SERDES" : "DPA_MODE==NONE"
       }
     },
+    "I_SERDES.ROOT_BANK_CLKMUX" : {
+      "rules" : {
+        "ROUTE_TO_FABRIC_CLK" : "__arg0__",
+        "DPA_MODE" : "__arg1__"
+      },
+      "results" : {
+        "__location__" : "__ROOT_BANK_MUX_LOCATION__",
+        "I_SERDES" : "ROOT_BANK_SRC==__AB__&DPA_MODE==__arg1__ --#MUX=__ROOT_BANK_MUX__"
+      }
+    },
+    "I_SERDES.ROOT_MUX" : {
+      "rules" : {
+        "ROUTE_TO_FABRIC_CLK" : "__arg0__"
+      },
+      "results" : {
+        "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left___arg0__",
+        "ROOT_MUX_SEL" : "__ROOT_MUX__"
+      }
+    },
     "O_SERDES.BYPASS" : {
       "rules" : {
         "WIDTH" : "__arg0__"
@@ -135,6 +154,13 @@
         "O_SERDES" : "DDR_MODE==SDR"
       }
     },
+    "O_SERDES_CLK.IO" : {
+      "rules" : {
+      },
+      "results" : {
+        "TX_CLOCK_IO" : "TX_clock_IO"
+      }
+    },
     "O_SERDES_CLK.CLK_PHASE" : {
       "rules" : {
         "CLOCK_PHASE" : "__argCLOCK_PHASE__"
@@ -191,11 +217,16 @@
         "pll_PLLEN" : "__pll_enable__"
       }
     },
-    "PLL.MUX0" : {
+    "PLL.ROOT_MUX0" : {
       "rules" : {
         "__connectivity__" : "CLK_OUT",
         "__index__" : "__argIndex{default:0}__",
         "OUT0_ROUTE_TO_FABRIC_CLK" : "__arg0__"
+      },
+      "results" : {
+        "__define__" : "parse_pll_root_mux",
+        "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left___arg0__",
+        "ROOT_MUX_SEL" : "__pll_root_mux_sel__"
       }
     },
     "PLL.ROOT_MUX1" : {
@@ -323,11 +354,19 @@
     "CLK_BUF.ROOT_BANK_CLKMUX" : {
       "rules" : {
         "ROUTE_TO_FABRIC_CLK" : "__arg0__"
+      },
+      "results" : {
+        "__location__" : "__ROOT_BANK_MUX_LOCATION__",
+        "CLK_BUF" : "ROOT_BANK_SRC==__AB__ --#MUX=__ROOT_BANK_MUX__"
       }
     },
     "CLK_BUF.ROOT_MUX" : {
       "rules" : {
         "ROUTE_TO_FABRIC_CLK" : "__arg0__"
+      },
+      "results" : {
+        "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left___arg0__",
+        "ROOT_MUX_SEL" : "__ROOT_MUX__"
       }
     }
   },
@@ -417,7 +456,7 @@
       "g_all_clock_pins = ['%s_CC_%s' % (i, j) for i in all_banks for j in cc_p_pin_list]",
       "g_all_pll_clock_pins = [pin for pin in g_all_clock_pins]",
       "g_boot_clock_resources = 0",
-      "g_pin_resources = []",
+      "g_pin_resources = {}",
       "g_fabric_clock_resources = 0",
       "g_pll_resources = []"
     ]
@@ -442,9 +481,13 @@
     "__check_pin_resource__" : {
       "__module__" : ["I_BUF", "O_BUF", "O_BUFT"],
       "__equation__" : [
-        "pin_result = '__location0__' not in g_pin_resources",
-        "g_pin_resources.append('__location0__' if pin_result else '')",
-        "g_pin_resources = [pin for pin in g_pin_resources if pin != '']" 
+        "temp = '__primitive_flags__'.split(',')",
+        "bidir = 'INOUT' in temp",
+        "value = 1 if 'I_BUF' in temp else 2",
+        "pin_result = '__location0__' not in g_pin_resources or ((g_pin_resources['__location0__'] & value) == 0)",
+        "exist = 0 if '__location0__' not in g_pin_resources else g_pin_resources['__location0__']",
+        "g_pin_resources['__location0__' if pin_result else ''] = exist | (value if bidir else 3)",
+        "g_pin_resources.pop('', None)"
       ]
     },
     "__ds_pin_is_valid__" : {
@@ -479,9 +522,10 @@
       "__equation__" : [
         "pin_result = '__location0__' not in g_pin_resources",
         "pin_result = pin_result and '__location1__' not in g_pin_resources",
-        "g_pin_resources.append('__location0__' if pin_result else '')",
-        "g_pin_resources.append('__location1__' if pin_result else '')",
-        "g_pin_resources = [pin for pin in g_pin_resources if pin != '']"
+        "g_pin_resources['__location0__' if pin_result else ''] = 3",
+        "g_pin_resources.pop('', None)",
+        "g_pin_resources['__location1__' if pin_result else ''] = 3",
+        "g_pin_resources.pop('', None)"
       ]
     },
     "__clock_pin_is_valid__" : {

diff --git a/tests/unittest/ModelConfig/design_edit.sdc b/tests/unittest/ModelConfig/design_edit.sdc
@@ -3,32 +3,33 @@
 # Fabric clock assignment
 #
 #############
-# This is fabric clock needed by logic but also primitive core clock
-# set_clock_pin -device_clock clk[0] -design_clock clk0 (Physical port name)
+# This clock need to route to fabric slot #0
+# set_clock_pin -device_clock clk[0] -design_clock clk0 (Physical port name, clock module: CLK_BUF $clkbuf$top.$ibuf_clk0)
 # set_clock_pin -device_clock clk[0] -design_clock $clk_buf_$ibuf_clk0 (Original clock primitive out-net to fabric)
 set_clock_pin   -device_clock clk[0] -design_clock $clk_buf_$ibuf_clk0
 
-# This is fabric clock needed by primitive core clock
-# set_clock_pin -device_clock clk[1] -design_clock clk1 (Physical port name)
+# This clock is only used by gearbox, does not need to route to fabric slot #1
+# set_clock_pin -device_clock clk[1] -design_clock clk1 (Physical port name, clock module: CLK_BUF clk_buf)
 
-# This is fabric clock needed by logic but also primitive core clock
-# set_clock_pin -device_clock clk[2] -design_clock clk1 (Physical port name)
-# set_clock_pin -device_clock clk[2] -design_clock pll_clk (Original clock primitive out-net to fabric)
-set_clock_pin   -device_clock clk[2] -design_clock pll_clk
+# This clock is only used by gearbox, does not need to route to fabric slot #2
+# set_clock_pin -device_clock clk[2] -design_clock clk1 (Physical port name, clock module: PLL pll)
 
-# This is fabric clock needed by primitive core clock
-# set_clock_pin -device_clock clk[3] -design_clock clk1 (Physical port name)
+# This clock need to route to fabric slot #3
+# set_clock_pin -device_clock clk[3] -design_clock clk2 (Physical port name, clock module: CLK_BUF $clkbuf$top.$ibuf_clk2)
+# set_clock_pin -device_clock clk[3] -design_clock $clk_buf_$ibuf_clk2 (Original clock primitive out-net to fabric)
+set_clock_pin   -device_clock clk[3] -design_clock $clk_buf_$ibuf_clk2
 
-# This is fabric clock needed by primitive core clock
-# set_clock_pin -device_clock clk[4] -design_clock BOOT_CLOCK#0 (Physical port name)
+# This clock need to route to fabric slot #4
+# set_clock_pin -device_clock clk[4] -design_clock din_serdes (Physical port name, clock module: I_SERDES i_serdes)
+# set_clock_pin -device_clock clk[4] -design_clock iserdes_clk_out (Original clock primitive out-net to fabric)
+set_clock_pin   -device_clock clk[4] -design_clock iserdes_clk_out
 
-# This is fabric clock needed by logic
-# set_clock_pin -device_clock clk[5] -design_clock clk2 (Physical port name)
-# set_clock_pin -device_clock clk[5] -design_clock $clk_buf_$ibuf_clk2 (Original clock primitive out-net to fabric)
-set_clock_pin   -device_clock clk[5] -design_clock $clk_buf_$ibuf_clk2
+# This clock is only used by gearbox, does not need to route to fabric slot #5
+# set_clock_pin -device_clock clk[5] -design_clock BOOT_CLOCK#0 (Physical port name, clock module: PLL pll_osc)
 
+# This clock need to route to fabric slot #6
 # This is fabric clock buffer
-# set_clock_pin -device_clock clk[6] -design_clock FABRIC_CLKBUF#0 (Physical port name)
+# set_clock_pin -device_clock clk[6] -design_clock FABRIC_CLKBUF#0 (Physical port name, clock module: FCLK_BUF $clkbuf$top.clk0_div)
 # set_clock_pin -device_clock clk[6] -design_clock $fclk_buf_clk0_div (Original clock primitive out-net to fabric)
 set_clock_pin   -device_clock clk[6] -design_clock $fclk_buf_clk0_div
 
@@ -575,59 +576,51 @@ set_io   $auto_520                        HP_1_4_2P      -mode MODE_BP_DDR_A_RX
 # Each gearbox core clock
 #
 #############
-# Clock module: CLK_BUF
-# Clock module name: $clkbuf$top.$ibuf_clk0
-# Clock port: O
-# Clock port net: $clk_buf_$ibuf_clk0
-# Primitive module: $ibuf$top.$ibuf_din
+# Module: I_DELAY
+# Name: i_delay
 # Location: HP_1_20_10P
+# Port: CLK_IN
+# Net: $clk_buf_$ibuf_clk0
+# Slot: 0
 set_core_clk HP_1_20_10P 0
 
-# Clock module: CLK_BUF
-# Clock module name: clk_buf
-# Clock port: O
-# Clock port net: clk1_buf
-# Primitive module: $obuf$top.$obuf_dout
-# Location: HP_2_20_10P
-set_core_clk HP_2_20_10P 1
-
-# Clock module: PLL
-# Clock module name: pll
-# Clock port: CLK_OUT
-# Clock port net: pll_clk
-# Primitive module: $ibuf$top.$ibuf_din_serdes
+# Module: I_SERDES
+# Name: i_serdes
 # Location: HR_2_0_0P
+# Port: CLK_IN
+# Net: pll_clk
+# Slot: 2
 set_core_clk HR_2_0_0P   2
 
-# Clock module: PLL
-# Clock module name: pll
-# Clock port: CLK_OUT
-# Clock port net: pll_clk
-# Primitive module: $obuf$top.$obuf_dout_serdes
+# Module: O_DELAY
+# Name: o_delay
+# Location: HP_2_20_10P
+# Port: CLK_IN
+# Net: clk1_buf
+# Slot: 1
+set_core_clk HP_2_20_10P 1
+
+# Module: O_SERDES
+# Name: o_serdes
 # Location: HR_2_2_1P
+# Port: CLK_IN
+# Net: pll_clk
+# Slot: 2
 set_core_clk HR_2_2_1P   2
 
-# Clock module: PLL
-# Clock module name: pll
-# Clock port: CLK_OUT
-# Clock port net: pll_clk
-# Primitive module: i_buf_ds
-# Location: HP_1_4_2P
-set_core_clk HP_1_4_2P   3
-
-# Clock module: PLL
-# Clock module name: pll
-# Clock port: CLK_OUT
-# Clock port net: pll_clk
-# Primitive module: o_buf_ds
+# Module: O_DDR
+# Name: o_ddr
 # Location: HP_1_8_4P
-set_core_clk HP_1_8_4P   3
+# Port: C
+# Net: pll_clk
+# Slot: 2
+set_core_clk HP_1_8_4P   2
 
-# Clock module: PLL
-# Clock module name: pll_osc
-# Clock port: CLK_OUT
-# Clock port net: osc_pll
-# Primitive module: o_buf_ds_osc
+# Module: O_DDR
+# Name: o_ddr_osc
 # Location: HP_2_22_11P
-set_core_clk HP_2_22_11P 4
+# Port: C
+# Net: osc_pll
+# Slot: 5
+set_core_clk HP_2_22_11P 5
 
diff --git a/tests/unittest/ModelConfig/golden/bitstream_setting.xml b/tests/unittest/ModelConfig/golden/bitstream_setting.xml
@@ -6,18 +6,13 @@
     <bit value="0" path="fpga_top.grid_io_bottom_13__1_.logical_tile_io_mode_io__0.mem_iopad_0_clk_0[1]"/>
     <bit value="0" path="fpga_top.grid_io_bottom_13__1_.logical_tile_io_mode_io__0.mem_iopad_0_clk_0[2]"/>
     <bit value="0" path="fpga_top.grid_io_bottom_13__1_.logical_tile_io_mode_io__0.mem_iopad_0_clk_0[3]"/>
-    <!-- Location: HP_1_4_2P, Value: 3, X: 5, Y: 1 -->
-    <bit value="1" path="fpga_top.grid_io_bottom_5__1_.logical_tile_io_mode_io__0.mem_iopad_0_clk_0[0]"/>
-    <bit value="1" path="fpga_top.grid_io_bottom_5__1_.logical_tile_io_mode_io__0.mem_iopad_0_clk_0[1]"/>
-    <bit value="0" path="fpga_top.grid_io_bottom_5__1_.logical_tile_io_mode_io__0.mem_iopad_0_clk_0[2]"/>
-    <bit value="0" path="fpga_top.grid_io_bottom_5__1_.logical_tile_io_mode_io__0.mem_iopad_0_clk_0[3]"/>
-    <!-- Location: HP_1_8_4P, Value: 3, X: 7, Y: 1 -->
-    <bit value="1" path="fpga_top.grid_io_bottom_7__1_.logical_tile_io_mode_io__0.mem_iopad_0_clk_0[0]"/>
+    <!-- Location: HP_1_8_4P, Value: 2, X: 7, Y: 1 -->
+    <bit value="0" path="fpga_top.grid_io_bottom_7__1_.logical_tile_io_mode_io__0.mem_iopad_0_clk_0[0]"/>
     <bit value="1" path="fpga_top.grid_io_bottom_7__1_.logical_tile_io_mode_io__0.mem_iopad_0_clk_0[1]"/>
     <bit value="0" path="fpga_top.grid_io_bottom_7__1_.logical_tile_io_mode_io__0.mem_iopad_0_clk_0[2]"/>
     <bit value="0" path="fpga_top.grid_io_bottom_7__1_.logical_tile_io_mode_io__0.mem_iopad_0_clk_0[3]"/>
     <!-- Unknown location: HP_2_20_10P, Value: 1, X: 0, Y: 0 -->
-    <!-- Unknown location: HP_2_22_11P, Value: 4, X: 0, Y: 0 -->
+    <!-- Unknown location: HP_2_22_11P, Value: 5, X: 0, Y: 0 -->
     <!-- Unknown location: HR_2_0_0P, Value: 2, X: 0, Y: 0 -->
     <!-- Unknown location: HR_2_2_1P, Value: 2, X: 0, Y: 0 -->
   </overwrite_bitstream>