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Merge pull request #43 from anaszameer/bram_update_testbench
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Bram update testbench
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@muhammadhamza15
muhammadhamza15 authored Jul 6, 2024
2 parents 65b6413 + e17b8db commit 05a92bf
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Showing 8 changed files with 190 additions and 115 deletions.
64 changes: 40 additions & 24 deletions models_customer/verilog/TDP_RAM18KX2.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -169,9 +169,11 @@ module TDP_RAM18KX2 #(
end
end
else
// verilator lint_off BLKANDNBLK
RPARITY_A1 <= 2'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_A1 <= 2'bx;
// verilator lint_on BLKANDNBLK
`endif

always @(posedge CLK_B1)
if (WEN_B1) begin
Expand Down Expand Up @@ -210,9 +212,11 @@ module TDP_RAM18KX2 #(
end
end
else
// verilator lint_off BLKANDNBLK
RPARITY_B1 <= 2'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_B1 <= 2'bx;
// verilator lint_on BLKANDNBLK
`endif
end
endgenerate

Expand Down Expand Up @@ -277,9 +281,11 @@ module TDP_RAM18KX2 #(
collision_a_read_flag = 0;
end
else
// verilator lint_off BLKANDNBLK
RDATA_A1 <= 16'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_A1 <= 16'bx;
// verilator lint_on BLKANDNBLK
`endif

always @(posedge CLK_B1)
if (WEN_B1) begin
Expand Down Expand Up @@ -328,9 +334,11 @@ module TDP_RAM18KX2 #(
collision_b_read_flag = 0;
end
else
// verilator lint_off BLKANDNBLK
RDATA_B1 <= 16'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_B1 <= 16'bx;
// verilator lint_on BLKANDNBLK
`endif

// Collision checking
always @(posedge collision_a_write_flag) begin
Expand Down Expand Up @@ -472,9 +480,11 @@ module TDP_RAM18KX2 #(
end
end
else
// verilator lint_off BLKANDNBLK
RPARITY_A2 <= 2'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_A2 <= 2'bx;
// verilator lint_on BLKANDNBLK
`endif

always @(posedge CLK_B2)
if (WEN_B2) begin
Expand Down Expand Up @@ -513,9 +523,11 @@ module TDP_RAM18KX2 #(
end
end
else
// verilator lint_off BLKANDNBLK
RPARITY_B2 <= 2'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_B2 <= 2'bx;
// verilator lint_on BLKANDNBLK
`endif
end
endgenerate

Expand Down Expand Up @@ -580,9 +592,11 @@ module TDP_RAM18KX2 #(
collision_a2_read_flag = 0;
end
else
// verilator lint_off BLKANDNBLK
RDATA_A2 <= 16'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_A2 <= 16'bx;
// verilator lint_on BLKANDNBLK
`endif

always @(posedge CLK_B2)
if (WEN_B2) begin
Expand Down Expand Up @@ -631,9 +645,11 @@ module TDP_RAM18KX2 #(
collision_b2_read_flag = 0;
end
else
// verilator lint_off BLKANDNBLK
RDATA_B2 <= 16'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_B2 <= 16'bx;
// verilator lint_on BLKANDNBLK
`endif

// Collision checking
always @(posedge collision_a2_write_flag) begin
Expand Down
33 changes: 21 additions & 12 deletions models_customer/verilog/TDP_RAM36K.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -141,9 +141,12 @@ module TDP_RAM36K #(
end
end
else
// verilator lint_off BLKANDNBLK
RPARITY_A <= 4'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_A <= 4'bx;
// verilator lint_on BLKANDNBLK
`endif


always @(posedge CLK_B)
if (WEN_B) begin
Expand Down Expand Up @@ -183,9 +186,11 @@ module TDP_RAM36K #(
end
end
else
// verilator lint_off BLKANDNBLK
RPARITY_B <= 4'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_B <= 4'bx;
// verilator lint_on BLKANDNBLK
`endif
end
endgenerate

Expand Down Expand Up @@ -249,9 +254,11 @@ module TDP_RAM36K #(
collision_a_read_flag = 0;
end
else
// verilator lint_off BLKANDNBLK
RDATA_A <= 32'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_A <= 32'bx;
// verilator lint_on BLKANDNBLK
`endif

always @(posedge CLK_B)
if (WEN_B) begin
Expand Down Expand Up @@ -298,9 +305,11 @@ module TDP_RAM36K #(
collision_b_read_flag = 0;
end
else
// verilator lint_off BLKANDNBLK
RDATA_B <= 32'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_B <= 32'bx;
// verilator lint_on BLKANDNBLK
`endif


/*
Expand Down
64 changes: 40 additions & 24 deletions models_internal/verilog/TDP_RAM18KX2.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -169,9 +169,11 @@ module TDP_RAM18KX2 #(
end
end
else
// verilator lint_off BLKANDNBLK
RPARITY_A1 <= 2'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_A1 <= 2'bx;
// verilator lint_on BLKANDNBLK
`endif

always @(posedge CLK_B1)
if (WEN_B1) begin
Expand Down Expand Up @@ -210,9 +212,11 @@ module TDP_RAM18KX2 #(
end
end
else
// verilator lint_off BLKANDNBLK
RPARITY_B1 <= 2'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_B1 <= 2'bx;
// verilator lint_on BLKANDNBLK
`endif
end
endgenerate

Expand Down Expand Up @@ -277,9 +281,11 @@ module TDP_RAM18KX2 #(
collision_a_read_flag = 0;
end
else
// verilator lint_off BLKANDNBLK
RDATA_A1 <= 16'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_A1 <= 16'bx;
// verilator lint_on BLKANDNBLK
`endif

always @(posedge CLK_B1)
if (WEN_B1) begin
Expand Down Expand Up @@ -328,9 +334,11 @@ module TDP_RAM18KX2 #(
collision_b_read_flag = 0;
end
else
// verilator lint_off BLKANDNBLK
RDATA_B1 <= 16'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_B1 <= 16'bx;
// verilator lint_on BLKANDNBLK
`endif

// Collision checking
always @(posedge collision_a_write_flag) begin
Expand Down Expand Up @@ -472,9 +480,11 @@ module TDP_RAM18KX2 #(
end
end
else
// verilator lint_off BLKANDNBLK
RPARITY_A2 <= 2'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_A2 <= 2'bx;
// verilator lint_on BLKANDNBLK
`endif

always @(posedge CLK_B2)
if (WEN_B2) begin
Expand Down Expand Up @@ -513,9 +523,11 @@ module TDP_RAM18KX2 #(
end
end
else
// verilator lint_off BLKANDNBLK
RPARITY_B2 <= 2'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_B2 <= 2'bx;
// verilator lint_on BLKANDNBLK
`endif
end
endgenerate

Expand Down Expand Up @@ -580,9 +592,11 @@ module TDP_RAM18KX2 #(
collision_a2_read_flag = 0;
end
else
// verilator lint_off BLKANDNBLK
RDATA_A2 <= 16'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_A2 <= 16'bx;
// verilator lint_on BLKANDNBLK
`endif

always @(posedge CLK_B2)
if (WEN_B2) begin
Expand Down Expand Up @@ -631,9 +645,11 @@ module TDP_RAM18KX2 #(
collision_b2_read_flag = 0;
end
else
// verilator lint_off BLKANDNBLK
RDATA_B2 <= 16'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_B2 <= 16'bx;
// verilator lint_on BLKANDNBLK
`endif

// Collision checking
always @(posedge collision_a2_write_flag) begin
Expand Down
33 changes: 21 additions & 12 deletions models_internal/verilog/TDP_RAM36K.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -141,9 +141,12 @@ module TDP_RAM36K #(
end
end
else
// verilator lint_off BLKANDNBLK
RPARITY_A <= 4'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_A <= 4'bx;
// verilator lint_on BLKANDNBLK
`endif


always @(posedge CLK_B)
if (WEN_B) begin
Expand Down Expand Up @@ -183,9 +186,11 @@ module TDP_RAM36K #(
end
end
else
// verilator lint_off BLKANDNBLK
RPARITY_B <= 4'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_B <= 4'bx;
// verilator lint_on BLKANDNBLK
`endif
end
endgenerate

Expand Down Expand Up @@ -249,9 +254,11 @@ module TDP_RAM36K #(
collision_a_read_flag = 0;
end
else
// verilator lint_off BLKANDNBLK
RDATA_A <= 32'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_A <= 32'bx;
// verilator lint_on BLKANDNBLK
`endif

always @(posedge CLK_B)
if (WEN_B) begin
Expand Down Expand Up @@ -298,9 +305,11 @@ module TDP_RAM36K #(
collision_b_read_flag = 0;
end
else
// verilator lint_off BLKANDNBLK
RDATA_B <= 32'bx;
// verilator lint_on BLKANDNBLK
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_B <= 32'bx;
// verilator lint_on BLKANDNBLK
`endif


/*
Expand Down
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